Commit e7674b8c authored by Mika Kuoppala's avatar Mika Kuoppala Committed by Jani Nikula

drm/i915/skl: Double RC6 WRL always on

WaRsDoubleRc6WrlWithCoarsePowerGating should
be enabled for all Skylakes. Make it so.

Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: default avatarSagar Arun Kamble <sagar.a.kamble@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1449505785-20812-2-git-send-email-mika.kuoppala@intel.comSigned-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 6686ece1
...@@ -4673,8 +4673,7 @@ static void gen9_enable_rc6(struct drm_device *dev) ...@@ -4673,8 +4673,7 @@ static void gen9_enable_rc6(struct drm_device *dev)
/* 2b: Program RC6 thresholds.*/ /* 2b: Program RC6 thresholds.*/
/* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */ /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
if (IS_SKYLAKE(dev) && !((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && if (IS_SKYLAKE(dev))
IS_SKL_REVID(dev, 0, SKL_REVID_E0)))
I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16); I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
else else
I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16); I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
......
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