Commit e793d8c6 authored by David S. Miller's avatar David S. Miller

sparc64: Fix bit twiddling in sparc_pmu_enable_event().

There was a serious disconnect in the logic happening in
sparc_pmu_disable_event() vs. sparc_pmu_enable_event().

Event disable is implemented by programming a NOP event into the PCR.

However, event enable was not reversing this operation.  Instead, it
was setting the User/Priv/Hypervisor trace enable bits.

That's not sparc_pmu_enable_event()'s job, that's what
sparc_pmu_enable() and sparc_pmu_disable() do .

The intent of sparc_pmu_enable_event() is clear, since it first clear
out the event type encoding field.  So fix this by OR'ing in the event
encoding rather than the trace enable bits.
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 916ca14a
...@@ -817,15 +817,17 @@ static u64 nop_for_index(int idx) ...@@ -817,15 +817,17 @@ static u64 nop_for_index(int idx)
static inline void sparc_pmu_enable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx) static inline void sparc_pmu_enable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx)
{ {
u64 val, mask = mask_for_index(idx); u64 enc, val, mask = mask_for_index(idx);
int pcr_index = 0; int pcr_index = 0;
if (sparc_pmu->num_pcrs > 1) if (sparc_pmu->num_pcrs > 1)
pcr_index = idx; pcr_index = idx;
enc = perf_event_get_enc(cpuc->events[idx]);
val = cpuc->pcr[pcr_index]; val = cpuc->pcr[pcr_index];
val &= ~mask; val &= ~mask;
val |= hwc->config; val |= event_encoding(enc, idx);
cpuc->pcr[pcr_index] = val; cpuc->pcr[pcr_index] = val;
pcr_ops->write_pcr(pcr_index, cpuc->pcr[pcr_index]); pcr_ops->write_pcr(pcr_index, cpuc->pcr[pcr_index]);
......
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