Skip to content
Projects
Groups
Snippets
Help
Loading...
Help
Support
Keyboard shortcuts
?
Submit feedback
Contribute to GitLab
Sign in / Register
Toggle navigation
L
linux
Project overview
Project overview
Details
Activity
Releases
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Issues
0
Issues
0
List
Boards
Labels
Milestones
Merge Requests
0
Merge Requests
0
Analytics
Analytics
Repository
Value Stream
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Create a new issue
Commits
Issue Boards
Open sidebar
nexedi
linux
Commits
e8d6d615
Commit
e8d6d615
authored
Jan 08, 2010
by
Dave Airlie
Browse files
Options
Browse Files
Download
Plain Diff
Merge remote branch 'korg/drm-radeon-testing' into drm-testing
parents
a3a06cb6
003e69f9
Changes
30
Expand all
Hide whitespace changes
Inline
Side-by-side
Showing
30 changed files
with
649 additions
and
468 deletions
+649
-468
drivers/gpu/drm/drm_crtc.c
drivers/gpu/drm/drm_crtc.c
+1
-0
drivers/gpu/drm/drm_irq.c
drivers/gpu/drm/drm_irq.c
+4
-1
drivers/gpu/drm/radeon/ObjectID.h
drivers/gpu/drm/radeon/ObjectID.h
+433
-368
drivers/gpu/drm/radeon/atombios_dp.c
drivers/gpu/drm/radeon/atombios_dp.c
+4
-2
drivers/gpu/drm/radeon/mkregtable.c
drivers/gpu/drm/radeon/mkregtable.c
+3
-1
drivers/gpu/drm/radeon/r100.c
drivers/gpu/drm/radeon/r100.c
+14
-9
drivers/gpu/drm/radeon/r300.c
drivers/gpu/drm/radeon/r300.c
+16
-1
drivers/gpu/drm/radeon/r420.c
drivers/gpu/drm/radeon/r420.c
+32
-0
drivers/gpu/drm/radeon/r520.c
drivers/gpu/drm/radeon/r520.c
+1
-0
drivers/gpu/drm/radeon/r600.c
drivers/gpu/drm/radeon/r600.c
+13
-8
drivers/gpu/drm/radeon/r600_blit_kms.c
drivers/gpu/drm/radeon/r600_blit_kms.c
+2
-2
drivers/gpu/drm/radeon/radeon.h
drivers/gpu/drm/radeon/radeon.h
+6
-3
drivers/gpu/drm/radeon/radeon_agp.c
drivers/gpu/drm/radeon/radeon_agp.c
+2
-4
drivers/gpu/drm/radeon/radeon_asic.h
drivers/gpu/drm/radeon/radeon_asic.h
+0
-12
drivers/gpu/drm/radeon/radeon_atombios.c
drivers/gpu/drm/radeon/radeon_atombios.c
+40
-1
drivers/gpu/drm/radeon/radeon_combios.c
drivers/gpu/drm/radeon/radeon_combios.c
+14
-0
drivers/gpu/drm/radeon/radeon_connectors.c
drivers/gpu/drm/radeon/radeon_connectors.c
+17
-6
drivers/gpu/drm/radeon/radeon_display.c
drivers/gpu/drm/radeon/radeon_display.c
+5
-2
drivers/gpu/drm/radeon/radeon_encoders.c
drivers/gpu/drm/radeon/radeon_encoders.c
+8
-6
drivers/gpu/drm/radeon/radeon_gem.c
drivers/gpu/drm/radeon/radeon_gem.c
+0
-2
drivers/gpu/drm/radeon/radeon_irq_kms.c
drivers/gpu/drm/radeon/radeon_irq_kms.c
+8
-2
drivers/gpu/drm/radeon/radeon_legacy_tv.c
drivers/gpu/drm/radeon/radeon_legacy_tv.c
+7
-7
drivers/gpu/drm/radeon/radeon_mode.h
drivers/gpu/drm/radeon/radeon_mode.h
+0
-26
drivers/gpu/drm/radeon/radeon_object.c
drivers/gpu/drm/radeon/radeon_object.c
+3
-2
drivers/gpu/drm/radeon/rs400.c
drivers/gpu/drm/radeon/rs400.c
+2
-0
drivers/gpu/drm/radeon/rs600.c
drivers/gpu/drm/radeon/rs600.c
+9
-1
drivers/gpu/drm/radeon/rs690.c
drivers/gpu/drm/radeon/rs690.c
+2
-0
drivers/gpu/drm/radeon/rv515.c
drivers/gpu/drm/radeon/rv515.c
+1
-0
drivers/gpu/drm/radeon/rv770.c
drivers/gpu/drm/radeon/rv770.c
+1
-2
include/drm/drm_mode.h
include/drm/drm_mode.h
+1
-0
No files found.
drivers/gpu/drm/drm_crtc.c
View file @
e8d6d615
...
...
@@ -158,6 +158,7 @@ static struct drm_conn_prop_enum_list drm_connector_enum_list[] =
{
DRM_MODE_CONNECTOR_HDMIA
,
"HDMI Type A"
,
0
},
{
DRM_MODE_CONNECTOR_HDMIB
,
"HDMI Type B"
,
0
},
{
DRM_MODE_CONNECTOR_TV
,
"TV"
,
0
},
{
DRM_MODE_CONNECTOR_eDP
,
"Embedded DisplayPort"
,
0
},
};
static
struct
drm_prop_enum_list
drm_encoder_enum_list
[]
=
...
...
drivers/gpu/drm/drm_irq.c
View file @
e8d6d615
...
...
@@ -115,6 +115,7 @@ void drm_vblank_cleanup(struct drm_device *dev)
dev
->
num_crtcs
=
0
;
}
EXPORT_SYMBOL
(
drm_vblank_cleanup
);
int
drm_vblank_init
(
struct
drm_device
*
dev
,
int
num_crtcs
)
{
...
...
@@ -163,7 +164,6 @@ int drm_vblank_init(struct drm_device *dev, int num_crtcs)
}
dev
->
vblank_disable_allowed
=
0
;
return
0
;
err:
...
...
@@ -493,6 +493,9 @@ EXPORT_SYMBOL(drm_vblank_off);
*/
void
drm_vblank_pre_modeset
(
struct
drm_device
*
dev
,
int
crtc
)
{
/* vblank is not initialized (IRQ not installed ?) */
if
(
!
dev
->
num_crtcs
)
return
;
/*
* To avoid all the problems that might happen if interrupts
* were enabled/disabled around or between these calls, we just
...
...
drivers/gpu/drm/radeon/ObjectID.h
View file @
e8d6d615
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/radeon/atombios_dp.c
View file @
e8d6d615
...
...
@@ -468,7 +468,8 @@ void radeon_dp_set_link_config(struct drm_connector *connector,
struct
radeon_connector
*
radeon_connector
;
struct
radeon_connector_atom_dig
*
dig_connector
;
if
(
connector
->
connector_type
!=
DRM_MODE_CONNECTOR_DisplayPort
)
if
((
connector
->
connector_type
!=
DRM_MODE_CONNECTOR_DisplayPort
)
||
(
connector
->
connector_type
!=
DRM_MODE_CONNECTOR_eDP
))
return
;
radeon_connector
=
to_radeon_connector
(
connector
);
...
...
@@ -582,7 +583,8 @@ void dp_link_train(struct drm_encoder *encoder,
u8
train_set
[
4
];
int
i
;
if
(
connector
->
connector_type
!=
DRM_MODE_CONNECTOR_DisplayPort
)
if
((
connector
->
connector_type
!=
DRM_MODE_CONNECTOR_DisplayPort
)
||
(
connector
->
connector_type
!=
DRM_MODE_CONNECTOR_eDP
))
return
;
if
(
!
radeon_encoder
->
enc_priv
)
...
...
drivers/gpu/drm/radeon/mkregtable.c
View file @
e8d6d615
...
...
@@ -661,8 +661,10 @@ static int parser_auth(struct table *t, const char *filename)
fseek
(
file
,
0
,
SEEK_SET
);
/* get header */
if
(
fgets
(
buf
,
1024
,
file
)
==
NULL
)
if
(
fgets
(
buf
,
1024
,
file
)
==
NULL
)
{
fclose
(
file
);
return
-
1
;
}
/* first line will contain the last register
* and gpu name */
...
...
drivers/gpu/drm/radeon/r100.c
View file @
e8d6d615
...
...
@@ -131,7 +131,8 @@ void r100_hpd_init(struct radeon_device *rdev)
break
;
}
}
r100_irq_set
(
rdev
);
if
(
rdev
->
irq
.
installed
)
r100_irq_set
(
rdev
);
}
void
r100_hpd_fini
(
struct
radeon_device
*
rdev
)
...
...
@@ -243,6 +244,11 @@ int r100_irq_set(struct radeon_device *rdev)
{
uint32_t
tmp
=
0
;
if
(
!
rdev
->
irq
.
installed
)
{
WARN
(
1
,
"Can't enable IRQ/MSI because no handler is installed.
\n
"
);
WREG32
(
R_000040_GEN_INT_CNTL
,
0
);
return
-
EINVAL
;
}
if
(
rdev
->
irq
.
sw_int
)
{
tmp
|=
RADEON_SW_INT_ENABLE
;
}
...
...
@@ -356,6 +362,11 @@ void r100_fence_ring_emit(struct radeon_device *rdev,
/* Wait until IDLE & CLEAN */
radeon_ring_write
(
rdev
,
PACKET0
(
0x1720
,
0
));
radeon_ring_write
(
rdev
,
(
1
<<
16
)
|
(
1
<<
17
));
radeon_ring_write
(
rdev
,
PACKET0
(
RADEON_HOST_PATH_CNTL
,
0
));
radeon_ring_write
(
rdev
,
rdev
->
config
.
r100
.
hdp_cntl
|
RADEON_HDP_READ_BUFFER_INVALIDATE
);
radeon_ring_write
(
rdev
,
PACKET0
(
RADEON_HOST_PATH_CNTL
,
0
));
radeon_ring_write
(
rdev
,
rdev
->
config
.
r100
.
hdp_cntl
);
/* Emit fence sequence & fire IRQ */
radeon_ring_write
(
rdev
,
PACKET0
(
rdev
->
fence_drv
.
scratch_reg
,
0
));
radeon_ring_write
(
rdev
,
fence
->
seq
);
...
...
@@ -1713,14 +1724,6 @@ void r100_gpu_init(struct radeon_device *rdev)
r100_hdp_reset
(
rdev
);
}
void
r100_hdp_flush
(
struct
radeon_device
*
rdev
)
{
u32
tmp
;
tmp
=
RREG32
(
RADEON_HOST_PATH_CNTL
);
tmp
|=
RADEON_HDP_READ_BUFFER_INVALIDATE
;
WREG32
(
RADEON_HOST_PATH_CNTL
,
tmp
);
}
void
r100_hdp_reset
(
struct
radeon_device
*
rdev
)
{
uint32_t
tmp
;
...
...
@@ -3313,6 +3316,7 @@ static int r100_startup(struct radeon_device *rdev)
}
/* Enable IRQ */
r100_irq_set
(
rdev
);
rdev
->
config
.
r100
.
hdp_cntl
=
RREG32
(
RADEON_HOST_PATH_CNTL
);
/* 1M ring buffer */
r
=
r100_cp_init
(
rdev
,
1024
*
1024
);
if
(
r
)
{
...
...
@@ -3371,6 +3375,7 @@ void r100_fini(struct radeon_device *rdev)
radeon_gem_fini
(
rdev
);
if
(
rdev
->
flags
&
RADEON_IS_PCI
)
r100_pci_gart_fini
(
rdev
);
radeon_agp_fini
(
rdev
);
radeon_irq_kms_fini
(
rdev
);
radeon_fence_driver_fini
(
rdev
);
radeon_bo_fini
(
rdev
);
...
...
drivers/gpu/drm/radeon/r300.c
View file @
e8d6d615
...
...
@@ -36,7 +36,15 @@
#include "rv350d.h"
#include "r300_reg_safe.h"
/* This files gather functions specifics to: r300,r350,rv350,rv370,rv380 */
/* This files gather functions specifics to: r300,r350,rv350,rv370,rv380
*
* GPU Errata:
* - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL
* using MMIO to flush host path read cache, this lead to HARDLOCKUP.
* However, scheduling such write to the ring seems harmless, i suspect
* the CP read collide with the flush somehow, or maybe the MC, hard to
* tell. (Jerome Glisse)
*/
/*
* rv370,rv380 PCIE GART
...
...
@@ -178,6 +186,11 @@ void r300_fence_ring_emit(struct radeon_device *rdev,
/* Wait until IDLE & CLEAN */
radeon_ring_write
(
rdev
,
PACKET0
(
0x1720
,
0
));
radeon_ring_write
(
rdev
,
(
1
<<
17
)
|
(
1
<<
16
)
|
(
1
<<
9
));
radeon_ring_write
(
rdev
,
PACKET0
(
RADEON_HOST_PATH_CNTL
,
0
));
radeon_ring_write
(
rdev
,
rdev
->
config
.
r300
.
hdp_cntl
|
RADEON_HDP_READ_BUFFER_INVALIDATE
);
radeon_ring_write
(
rdev
,
PACKET0
(
RADEON_HOST_PATH_CNTL
,
0
));
radeon_ring_write
(
rdev
,
rdev
->
config
.
r300
.
hdp_cntl
);
/* Emit fence sequence & fire IRQ */
radeon_ring_write
(
rdev
,
PACKET0
(
rdev
->
fence_drv
.
scratch_reg
,
0
));
radeon_ring_write
(
rdev
,
fence
->
seq
);
...
...
@@ -1258,6 +1271,7 @@ static int r300_startup(struct radeon_device *rdev)
}
/* Enable IRQ */
r100_irq_set
(
rdev
);
rdev
->
config
.
r300
.
hdp_cntl
=
RREG32
(
RADEON_HOST_PATH_CNTL
);
/* 1M ring buffer */
r
=
r100_cp_init
(
rdev
,
1024
*
1024
);
if
(
r
)
{
...
...
@@ -1322,6 +1336,7 @@ void r300_fini(struct radeon_device *rdev)
rv370_pcie_gart_fini
(
rdev
);
if
(
rdev
->
flags
&
RADEON_IS_PCI
)
r100_pci_gart_fini
(
rdev
);
radeon_agp_fini
(
rdev
);
radeon_irq_kms_fini
(
rdev
);
radeon_fence_driver_fini
(
rdev
);
radeon_bo_fini
(
rdev
);
...
...
drivers/gpu/drm/radeon/r420.c
View file @
e8d6d615
...
...
@@ -30,6 +30,7 @@
#include "radeon_reg.h"
#include "radeon.h"
#include "atom.h"
#include "r100d.h"
#include "r420d.h"
int
r420_mc_init
(
struct
radeon_device
*
rdev
)
...
...
@@ -165,6 +166,34 @@ static void r420_clock_resume(struct radeon_device *rdev)
WREG32_PLL
(
R_00000D_SCLK_CNTL
,
sclk_cntl
);
}
static
void
r420_cp_errata_init
(
struct
radeon_device
*
rdev
)
{
/* RV410 and R420 can lock up if CP DMA to host memory happens
* while the 2D engine is busy.
*
* The proper workaround is to queue a RESYNC at the beginning
* of the CP init, apparently.
*/
radeon_scratch_get
(
rdev
,
&
rdev
->
config
.
r300
.
resync_scratch
);
radeon_ring_lock
(
rdev
,
8
);
radeon_ring_write
(
rdev
,
PACKET0
(
R300_CP_RESYNC_ADDR
,
1
));
radeon_ring_write
(
rdev
,
rdev
->
config
.
r300
.
resync_scratch
);
radeon_ring_write
(
rdev
,
0xDEADBEEF
);
radeon_ring_unlock_commit
(
rdev
);
}
static
void
r420_cp_errata_fini
(
struct
radeon_device
*
rdev
)
{
/* Catch the RESYNC we dispatched all the way back,
* at the very beginning of the CP init.
*/
radeon_ring_lock
(
rdev
,
8
);
radeon_ring_write
(
rdev
,
PACKET0
(
R300_RB3D_DSTCACHE_CTLSTAT
,
0
));
radeon_ring_write
(
rdev
,
R300_RB3D_DC_FINISH
);
radeon_ring_unlock_commit
(
rdev
);
radeon_scratch_free
(
rdev
,
rdev
->
config
.
r300
.
resync_scratch
);
}
static
int
r420_startup
(
struct
radeon_device
*
rdev
)
{
int
r
;
...
...
@@ -190,12 +219,14 @@ static int r420_startup(struct radeon_device *rdev)
r420_pipes_init
(
rdev
);
/* Enable IRQ */
r100_irq_set
(
rdev
);
rdev
->
config
.
r300
.
hdp_cntl
=
RREG32
(
RADEON_HOST_PATH_CNTL
);
/* 1M ring buffer */
r
=
r100_cp_init
(
rdev
,
1024
*
1024
);
if
(
r
)
{
dev_err
(
rdev
->
dev
,
"failled initializing CP (%d).
\n
"
,
r
);
return
r
;
}
r420_cp_errata_init
(
rdev
);
r
=
r100_wb_init
(
rdev
);
if
(
r
)
{
dev_err
(
rdev
->
dev
,
"failled initializing WB (%d).
\n
"
,
r
);
...
...
@@ -238,6 +269,7 @@ int r420_resume(struct radeon_device *rdev)
int
r420_suspend
(
struct
radeon_device
*
rdev
)
{
r420_cp_errata_fini
(
rdev
);
r100_cp_disable
(
rdev
);
r100_wb_disable
(
rdev
);
r100_irq_disable
(
rdev
);
...
...
drivers/gpu/drm/radeon/r520.c
View file @
e8d6d615
...
...
@@ -186,6 +186,7 @@ static int r520_startup(struct radeon_device *rdev)
}
/* Enable IRQ */
rs600_irq_set
(
rdev
);
rdev
->
config
.
r300
.
hdp_cntl
=
RREG32
(
RADEON_HOST_PATH_CNTL
);
/* 1M ring buffer */
r
=
r100_cp_init
(
rdev
,
1024
*
1024
);
if
(
r
)
{
...
...
drivers/gpu/drm/radeon/r600.c
View file @
e8d6d615
...
...
@@ -285,7 +285,8 @@ void r600_hpd_init(struct radeon_device *rdev)
}
}
}
r600_irq_set
(
rdev
);
if
(
rdev
->
irq
.
installed
)
r600_irq_set
(
rdev
);
}
void
r600_hpd_fini
(
struct
radeon_device
*
rdev
)
...
...
@@ -726,6 +727,10 @@ int r600_mc_init(struct radeon_device *rdev)
a
.
full
=
rfixed_const
(
100
);
rdev
->
pm
.
sclk
.
full
=
rfixed_const
(
rdev
->
clock
.
default_sclk
);
rdev
->
pm
.
sclk
.
full
=
rfixed_div
(
rdev
->
pm
.
sclk
,
a
);
if
(
rdev
->
flags
&
RADEON_IS_IGP
)
rdev
->
mc
.
igp_sideport_enabled
=
radeon_atombios_sideport_present
(
rdev
);
return
0
;
}
...
...
@@ -1384,11 +1389,6 @@ void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
(
void
)
RREG32
(
PCIE_PORT_DATA
);
}
void
r600_hdp_flush
(
struct
radeon_device
*
rdev
)
{
WREG32
(
R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL
,
0x1
);
}
/*
* CP & Ring
*/
...
...
@@ -1785,6 +1785,8 @@ void r600_fence_ring_emit(struct radeon_device *rdev,
radeon_ring_write
(
rdev
,
PACKET3
(
PACKET3_SET_CONFIG_REG
,
1
));
radeon_ring_write
(
rdev
,
((
rdev
->
fence_drv
.
scratch_reg
-
PACKET3_SET_CONFIG_REG_OFFSET
)
>>
2
));
radeon_ring_write
(
rdev
,
fence
->
seq
);
radeon_ring_write
(
rdev
,
PACKET0
(
R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL
,
0
));
radeon_ring_write
(
rdev
,
1
);
/* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
radeon_ring_write
(
rdev
,
PACKET0
(
CP_INT_STATUS
,
0
));
radeon_ring_write
(
rdev
,
RB_INT_STAT
);
...
...
@@ -2089,8 +2091,7 @@ void r600_fini(struct radeon_device *rdev)
radeon_gem_fini
(
rdev
);
radeon_fence_driver_fini
(
rdev
);
radeon_clocks_fini
(
rdev
);
if
(
rdev
->
flags
&
RADEON_IS_AGP
)
radeon_agp_fini
(
rdev
);
radeon_agp_fini
(
rdev
);
radeon_bo_fini
(
rdev
);
radeon_atombios_fini
(
rdev
);
kfree
(
rdev
->
bios
);
...
...
@@ -2461,6 +2462,10 @@ int r600_irq_set(struct radeon_device *rdev)
u32
mode_int
=
0
;
u32
hpd1
,
hpd2
,
hpd3
,
hpd4
=
0
,
hpd5
=
0
,
hpd6
=
0
;
if
(
!
rdev
->
irq
.
installed
)
{
WARN
(
1
,
"Can't enable IRQ/MSI because no handler is installed.
\n
"
);
return
-
EINVAL
;
}
/* don't enable anything if the ih is disabled */
if
(
!
rdev
->
ih
.
enabled
)
return
0
;
...
...
drivers/gpu/drm/radeon/r600_blit_kms.c
View file @
e8d6d615
...
...
@@ -577,9 +577,9 @@ int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
ring_size
=
num_loops
*
dwords_per_loop
;
/* set default + shaders */
ring_size
+=
40
;
/* shaders + def state */
ring_size
+=
5
;
/* fence emit for VB IB */
ring_size
+=
7
;
/* fence emit for VB IB */
ring_size
+=
5
;
/* done copy */
ring_size
+=
5
;
/* fence emit for done copy */
ring_size
+=
7
;
/* fence emit for done copy */
r
=
radeon_ring_lock
(
rdev
,
ring_size
);
WARN_ON
(
r
);
...
...
drivers/gpu/drm/radeon/radeon.h
View file @
e8d6d615
...
...
@@ -319,10 +319,12 @@ struct radeon_mc {
u64
real_vram_size
;
int
vram_mtrr
;
bool
vram_is_ddr
;
bool
igp_sideport_enabled
;
};
int
radeon_mc_setup
(
struct
radeon_device
*
rdev
);
bool
radeon_combios_sideport_present
(
struct
radeon_device
*
rdev
);
bool
radeon_atombios_sideport_present
(
struct
radeon_device
*
rdev
);
/*
* GPU scratch registers structures, functions & helpers
...
...
@@ -654,7 +656,6 @@ struct radeon_asic {
uint32_t
offset
,
uint32_t
obj_size
);
int
(
*
clear_surface_reg
)(
struct
radeon_device
*
rdev
,
int
reg
);
void
(
*
bandwidth_update
)(
struct
radeon_device
*
rdev
);
void
(
*
hdp_flush
)(
struct
radeon_device
*
rdev
);
void
(
*
hpd_init
)(
struct
radeon_device
*
rdev
);
void
(
*
hpd_fini
)(
struct
radeon_device
*
rdev
);
bool
(
*
hpd_sense
)(
struct
radeon_device
*
rdev
,
enum
radeon_hpd_id
hpd
);
...
...
@@ -667,11 +668,14 @@ struct radeon_asic {
struct
r100_asic
{
const
unsigned
*
reg_safe_bm
;
unsigned
reg_safe_bm_size
;
u32
hdp_cntl
;
};
struct
r300_asic
{
const
unsigned
*
reg_safe_bm
;
unsigned
reg_safe_bm_size
;
u32
resync_scratch
;
u32
hdp_cntl
;
};
struct
r600_asic
{
...
...
@@ -1007,7 +1011,6 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
#define radeon_hdp_flush(rdev) (rdev)->asic->hdp_flush((rdev))
#define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
#define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
#define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
...
...
drivers/gpu/drm/radeon/radeon_agp.c
View file @
e8d6d615
...
...
@@ -252,10 +252,8 @@ void radeon_agp_resume(struct radeon_device *rdev)
void
radeon_agp_fini
(
struct
radeon_device
*
rdev
)
{
#if __OS_HAS_AGP
if
(
rdev
->
flags
&
RADEON_IS_AGP
)
{
if
(
rdev
->
ddev
->
agp
&&
rdev
->
ddev
->
agp
->
acquired
)
{
drm_agp_release
(
rdev
->
ddev
);
}
if
(
rdev
->
ddev
->
agp
&&
rdev
->
ddev
->
agp
->
acquired
)
{
drm_agp_release
(
rdev
->
ddev
);
}
#endif
}
drivers/gpu/drm/radeon/radeon_asic.h
View file @
e8d6d615
...
...
@@ -77,7 +77,6 @@ int r100_clear_surface_reg(struct radeon_device *rdev, int reg);
void
r100_bandwidth_update
(
struct
radeon_device
*
rdev
);
void
r100_ring_ib_execute
(
struct
radeon_device
*
rdev
,
struct
radeon_ib
*
ib
);
int
r100_ring_test
(
struct
radeon_device
*
rdev
);
void
r100_hdp_flush
(
struct
radeon_device
*
rdev
);
void
r100_hpd_init
(
struct
radeon_device
*
rdev
);
void
r100_hpd_fini
(
struct
radeon_device
*
rdev
);
bool
r100_hpd_sense
(
struct
radeon_device
*
rdev
,
enum
radeon_hpd_id
hpd
);
...
...
@@ -114,7 +113,6 @@ static struct radeon_asic r100_asic = {
.
set_surface_reg
=
r100_set_surface_reg
,
.
clear_surface_reg
=
r100_clear_surface_reg
,
.
bandwidth_update
=
&
r100_bandwidth_update
,
.
hdp_flush
=
&
r100_hdp_flush
,
.
hpd_init
=
&
r100_hpd_init
,
.
hpd_fini
=
&
r100_hpd_fini
,
.
hpd_sense
=
&
r100_hpd_sense
,
...
...
@@ -174,7 +172,6 @@ static struct radeon_asic r300_asic = {
.
set_surface_reg
=
r100_set_surface_reg
,
.
clear_surface_reg
=
r100_clear_surface_reg
,
.
bandwidth_update
=
&
r100_bandwidth_update
,
.
hdp_flush
=
&
r100_hdp_flush
,
.
hpd_init
=
&
r100_hpd_init
,
.
hpd_fini
=
&
r100_hpd_fini
,
.
hpd_sense
=
&
r100_hpd_sense
,
...
...
@@ -218,7 +215,6 @@ static struct radeon_asic r420_asic = {
.
set_surface_reg
=
r100_set_surface_reg
,
.
clear_surface_reg
=
r100_clear_surface_reg
,
.
bandwidth_update
=
&
r100_bandwidth_update
,
.
hdp_flush
=
&
r100_hdp_flush
,
.
hpd_init
=
&
r100_hpd_init
,
.
hpd_fini
=
&
r100_hpd_fini
,
.
hpd_sense
=
&
r100_hpd_sense
,
...
...
@@ -267,7 +263,6 @@ static struct radeon_asic rs400_asic = {
.
set_surface_reg
=
r100_set_surface_reg
,
.
clear_surface_reg
=
r100_clear_surface_reg
,
.
bandwidth_update
=
&
r100_bandwidth_update
,
.
hdp_flush
=
&
r100_hdp_flush
,
.
hpd_init
=
&
r100_hpd_init
,
.
hpd_fini
=
&
r100_hpd_fini
,
.
hpd_sense
=
&
r100_hpd_sense
,
...
...
@@ -324,7 +319,6 @@ static struct radeon_asic rs600_asic = {
.
set_pcie_lanes
=
NULL
,
.
set_clock_gating
=
&
radeon_atom_set_clock_gating
,
.
bandwidth_update
=
&
rs600_bandwidth_update
,
.
hdp_flush
=
&
r100_hdp_flush
,
.
hpd_init
=
&
rs600_hpd_init
,
.
hpd_fini
=
&
rs600_hpd_fini
,
.
hpd_sense
=
&
rs600_hpd_sense
,
...
...
@@ -372,7 +366,6 @@ static struct radeon_asic rs690_asic = {
.
set_surface_reg
=
r100_set_surface_reg
,
.
clear_surface_reg
=
r100_clear_surface_reg
,
.
bandwidth_update
=
&
rs690_bandwidth_update
,
.
hdp_flush
=
&
r100_hdp_flush
,
.
hpd_init
=
&
rs600_hpd_init
,
.
hpd_fini
=
&
rs600_hpd_fini
,
.
hpd_sense
=
&
rs600_hpd_sense
,
...
...
@@ -424,7 +417,6 @@ static struct radeon_asic rv515_asic = {
.
set_surface_reg
=
r100_set_surface_reg
,
.
clear_surface_reg
=
r100_clear_surface_reg
,
.
bandwidth_update
=
&
rv515_bandwidth_update
,
.
hdp_flush
=
&
r100_hdp_flush
,
.
hpd_init
=
&
rs600_hpd_init
,
.
hpd_fini
=
&
rs600_hpd_fini
,
.
hpd_sense
=
&
rs600_hpd_sense
,
...
...
@@ -467,7 +459,6 @@ static struct radeon_asic r520_asic = {
.
set_surface_reg
=
r100_set_surface_reg
,
.
clear_surface_reg
=
r100_clear_surface_reg
,
.
bandwidth_update
=
&
rv515_bandwidth_update
,
.
hdp_flush
=
&
r100_hdp_flush
,
.
hpd_init
=
&
rs600_hpd_init
,
.
hpd_fini
=
&
rs600_hpd_fini
,
.
hpd_sense
=
&
rs600_hpd_sense
,
...
...
@@ -508,7 +499,6 @@ int r600_ring_test(struct radeon_device *rdev);
int
r600_copy_blit
(
struct
radeon_device
*
rdev
,
uint64_t
src_offset
,
uint64_t
dst_offset
,
unsigned
num_pages
,
struct
radeon_fence
*
fence
);
void
r600_hdp_flush
(
struct
radeon_device
*
rdev
);
void
r600_hpd_init
(
struct
radeon_device
*
rdev
);
void
r600_hpd_fini
(
struct
radeon_device
*
rdev
);
bool
r600_hpd_sense
(
struct
radeon_device
*
rdev
,
enum
radeon_hpd_id
hpd
);
...
...
@@ -544,7 +534,6 @@ static struct radeon_asic r600_asic = {
.
set_surface_reg
=
r600_set_surface_reg
,
.
clear_surface_reg
=
r600_clear_surface_reg
,
.
bandwidth_update
=
&
rv515_bandwidth_update
,
.
hdp_flush
=
&
r600_hdp_flush
,
.
hpd_init
=
&
r600_hpd_init
,
.
hpd_fini
=
&
r600_hpd_fini
,
.
hpd_sense
=
&
r600_hpd_sense
,
...
...
@@ -589,7 +578,6 @@ static struct radeon_asic rv770_asic = {
.
set_surface_reg
=
r600_set_surface_reg
,
.
clear_surface_reg
=
r600_clear_surface_reg
,
.
bandwidth_update
=
&
rv515_bandwidth_update
,
.
hdp_flush
=
&
r600_hdp_flush
,
.
hpd_init
=
&
r600_hpd_init
,
.
hpd_fini
=
&
r600_hpd_fini
,
.
hpd_sense
=
&
r600_hpd_sense
,
...
...
drivers/gpu/drm/radeon/radeon_atombios.c
View file @
e8d6d615
...
...
@@ -346,7 +346,9 @@ const int object_connector_convert[] = {
DRM_MODE_CONNECTOR_Unknown
,
DRM_MODE_CONNECTOR_Unknown
,
DRM_MODE_CONNECTOR_Unknown
,
DRM_MODE_CONNECTOR_DisplayPort
DRM_MODE_CONNECTOR_DisplayPort
,
DRM_MODE_CONNECTOR_eDP
,
DRM_MODE_CONNECTOR_Unknown
};
bool
radeon_get_atom_connector_info_from_object_table
(
struct
drm_device
*
dev
)
...
...
@@ -936,6 +938,43 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
return
false
;
}
union
igp_info
{
struct
_ATOM_INTEGRATED_SYSTEM_INFO
info
;
struct
_ATOM_INTEGRATED_SYSTEM_INFO_V2
info_2
;
};
bool
radeon_atombios_sideport_present
(
struct
radeon_device
*
rdev
)
{
struct
radeon_mode_info
*
mode_info
=
&
rdev
->
mode_info
;
int
index
=
GetIndexIntoMasterTable
(
DATA
,
IntegratedSystemInfo
);
union
igp_info
*
igp_info
;
u8
frev
,
crev
;
u16
data_offset
;
atom_parse_data_header
(
mode_info
->
atom_context
,
index
,
NULL
,
&
frev
,
&
crev
,
&
data_offset
);
igp_info
=
(
union
igp_info
*
)(
mode_info
->
atom_context
->
bios
+
data_offset
);
if
(
igp_info
)
{
switch
(
crev
)
{
case
1
:
if
(
igp_info
->
info
.
ucMemoryType
&
0xf0
)
return
true
;
break
;
case
2
:
if
(
igp_info
->
info_2
.
ucMemoryType
&
0x0f
)
return
true
;
break
;
default:
DRM_ERROR
(
"Unsupported IGP table: %d %d
\n
"
,
frev
,
crev
);
break
;
}
}
return
false
;
}
bool
radeon_atombios_get_tmds_info
(
struct
radeon_encoder
*
encoder
,
struct
radeon_encoder_int_tmds
*
tmds
)
{
...
...
drivers/gpu/drm/radeon/radeon_combios.c
View file @
e8d6d615
...
...
@@ -595,6 +595,20 @@ bool radeon_combios_get_clock_info(struct drm_device *dev)
return
false
;
}
bool
radeon_combios_sideport_present
(
struct
radeon_device
*
rdev
)
{
struct
drm_device
*
dev
=
rdev
->
ddev
;
u16
igp_info
;
igp_info
=
combios_get_table_offset
(
dev
,
COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE
);
if
(
igp_info
)
{
if
(
RBIOS16
(
igp_info
+
0x4
))
return
true
;
}
return
false
;
}
static
const
uint32_t
default_primarydac_adj
[
CHIP_LAST
]
=
{
0x00000808
,
/* r100 */
0x00000808
,
/* rv100 */
...
...
drivers/gpu/drm/radeon/radeon_connectors.c
View file @
e8d6d615
...
...
@@ -49,8 +49,10 @@ void radeon_connector_hotplug(struct drm_connector *connector)
if
(
radeon_connector
->
hpd
.
hpd
!=
RADEON_HPD_NONE
)
radeon_hpd_set_polarity
(
rdev
,
radeon_connector
->
hpd
.
hpd
);
if
(
connector
->
connector_type
==
DRM_MODE_CONNECTOR_DisplayPort
)
{
if
(
radeon_dp_getsinktype
(
radeon_connector
)
==
CONNECTOR_OBJECT_ID_DISPLAYPORT
)
{
if
((
connector
->
connector_type
==
DRM_MODE_CONNECTOR_DisplayPort
)
||
(
connector
->
connector_type
==
DRM_MODE_CONNECTOR_eDP
))
{
if
((
radeon_dp_getsinktype
(
radeon_connector
)
==
CONNECTOR_OBJECT_ID_DISPLAYPORT
)
||
(
radeon_dp_getsinktype
(
radeon_connector
)
==
CONNECTOR_OBJECT_ID_eDP
))
{
if
(
radeon_dp_needs_link_train
(
radeon_connector
))
{
if
(
connector
->
encoder
)
dp_link_train
(
connector
->
encoder
,
connector
);
...
...
@@ -967,7 +969,8 @@ static enum drm_connector_status radeon_dp_detect(struct drm_connector *connecto
}
sink_type
=
radeon_dp_getsinktype
(
radeon_connector
);
if
(
sink_type
==
CONNECTOR_OBJECT_ID_DISPLAYPORT
)
{
if
((
sink_type
==
CONNECTOR_OBJECT_ID_DISPLAYPORT
)
||
(
sink_type
==
CONNECTOR_OBJECT_ID_eDP
))
{
if
(
radeon_dp_getdpcd
(
radeon_connector
))
{
radeon_dig_connector
->
dp_sink_type
=
sink_type
;
ret
=
connector_status_connected
;
...
...
@@ -992,7 +995,8 @@ static int radeon_dp_mode_valid(struct drm_connector *connector,
/* XXX check mode bandwidth */
if
(
radeon_dig_connector
->
dp_sink_type
==
CONNECTOR_OBJECT_ID_DISPLAYPORT
)
if
((
radeon_dig_connector
->
dp_sink_type
==
CONNECTOR_OBJECT_ID_DISPLAYPORT
)
||
(
radeon_dig_connector
->
dp_sink_type
==
CONNECTOR_OBJECT_ID_eDP
))
return
radeon_dp_mode_valid_helper
(
radeon_connector
,
mode
);
else
return
MODE_OK
;
...
...
@@ -1145,6 +1149,7 @@ radeon_add_atom_connector(struct drm_device *dev,
subpixel_order
=
SubPixelHorizontalRGB
;
break
;
case
DRM_MODE_CONNECTOR_DisplayPort
:
case
DRM_MODE_CONNECTOR_eDP
:
radeon_dig_connector
=
kzalloc
(
sizeof
(
struct
radeon_connector_atom_dig
),
GFP_KERNEL
);
if
(
!
radeon_dig_connector
)
goto
failed
;
...
...
@@ -1157,10 +1162,16 @@ radeon_add_atom_connector(struct drm_device *dev,
goto
failed
;
if
(
i2c_bus
->
valid
)
{
/* add DP i2c bus */
radeon_dig_connector
->
dp_i2c_bus
=
radeon_i2c_create_dp
(
dev
,
i2c_bus
,
"DP-auxch"
);
if
(
connector_type
==
DRM_MODE_CONNECTOR_eDP
)
radeon_dig_connector
->
dp_i2c_bus
=
radeon_i2c_create_dp
(
dev
,
i2c_bus
,
"eDP-auxch"
);
else
radeon_dig_connector
->
dp_i2c_bus
=
radeon_i2c_create_dp
(
dev
,
i2c_bus
,
"DP-auxch"
);
if
(
!
radeon_dig_connector
->
dp_i2c_bus
)
goto
failed
;
radeon_connector
->
ddc_bus
=
radeon_i2c_create
(
dev
,
i2c_bus
,
"DP"
);
if
(
connector_type
==
DRM_MODE_CONNECTOR_eDP
)
radeon_connector
->
ddc_bus
=
radeon_i2c_create
(
dev
,
i2c_bus
,
"eDP"
);
else
radeon_connector
->
ddc_bus
=
radeon_i2c_create
(
dev
,
i2c_bus
,
"DP"
);
if
(
!
radeon_connector
->
ddc_bus
)
goto
failed
;
}
...
...
drivers/gpu/drm/radeon/radeon_display.c
View file @
e8d6d615
...
...
@@ -234,7 +234,7 @@ static const char *encoder_names[34] = {
"INTERNAL_UNIPHY2"
,
};
static
const
char
*
connector_names
[
1
3
]
=
{
static
const
char
*
connector_names
[
1
5
]
=
{
"Unknown"
,
"VGA"
,
"DVI-I"
,
...
...
@@ -248,6 +248,8 @@ static const char *connector_names[13] = {
"DisplayPort"
,
"HDMI-A"
,
"HDMI-B"
,
"TV"
,
"eDP"
,
};
static
const
char
*
hpd_names
[
7
]
=
{
...
...
@@ -352,7 +354,8 @@ int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
{
int
ret
=
0
;
if
(
radeon_connector
->
base
.
connector_type
==
DRM_MODE_CONNECTOR_DisplayPort
)
{
if
((
radeon_connector
->
base
.
connector_type
==
DRM_MODE_CONNECTOR_DisplayPort
)
||
(
radeon_connector
->
base
.
connector_type
==
DRM_MODE_CONNECTOR_eDP
))
{
struct
radeon_connector_atom_dig
*
dig
=
radeon_connector
->
con_priv
;
if
(
dig
->
dp_i2c_bus
)
radeon_connector
->
edid
=
drm_get_edid
(
&
radeon_connector
->
base
,
&
dig
->
dp_i2c_bus
->
adapter
);
...
...
drivers/gpu/drm/radeon/radeon_encoders.c
View file @
e8d6d615
...
...
@@ -596,21 +596,23 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
return
ATOM_ENCODER_MODE_LVDS
;
break
;
case
DRM_MODE_CONNECTOR_DisplayPort
:
case
DRM_MODE_CONNECTOR_eDP
:
radeon_dig_connector
=
radeon_connector
->
con_priv
;
if
(
radeon_dig_connector
->
dp_sink_type
==
CONNECTOR_OBJECT_ID_DISPLAYPORT
)
if
((
radeon_dig_connector
->
dp_sink_type
==
CONNECTOR_OBJECT_ID_DISPLAYPORT
)
||
(
radeon_dig_connector
->
dp_sink_type
==
CONNECTOR_OBJECT_ID_eDP
))
return
ATOM_ENCODER_MODE_DP
;
else
if
(
drm_detect_hdmi_monitor
(
radeon_connector
->
edid
))
return
ATOM_ENCODER_MODE_HDMI
;
else
return
ATOM_ENCODER_MODE_DVI
;
break
;
case
CONNECTOR_DVI_
A
:
case
CONNECTOR_VGA
:
case
DRM_MODE_CONNECTOR_DVI
A
:
case
DRM_MODE_
CONNECTOR_VGA
:
return
ATOM_ENCODER_MODE_CRT
;
break
;
case
CONNECTOR_STV
:
case
CONNECTOR_CTV
:
case
CONNECTOR_
DIN
:
case
DRM_MODE_CONNECTOR_Composite
:
case
DRM_MODE_CONNECTOR_SVIDEO
:
case
DRM_MODE_CONNECTOR_9Pin
DIN
:
/* fix me */
return
ATOM_ENCODER_MODE_TV
;
/*return ATOM_ENCODER_MODE_CV;*/
...
...
drivers/gpu/drm/radeon/radeon_gem.c
View file @
e8d6d615
...
...
@@ -131,7 +131,6 @@ int radeon_gem_set_domain(struct drm_gem_object *gobj,
printk
(
KERN_ERR
"Failed to wait for object !
\n
"
);
return
r
;
}
radeon_hdp_flush
(
robj
->
rdev
);
}
return
0
;
}
...
...
@@ -312,7 +311,6 @@ int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
mutex_lock
(
&
dev
->
struct_mutex
);
drm_gem_object_unreference
(
gobj
);
mutex_unlock
(
&
dev
->
struct_mutex
);
radeon_hdp_flush
(
robj
->
rdev
);
return
r
;
}
...
...
drivers/gpu/drm/radeon/radeon_irq_kms.c
View file @
e8d6d615
...
...
@@ -97,6 +97,7 @@ void radeon_driver_irq_uninstall_kms(struct drm_device *dev)
rdev
->
irq
.
sw_int
=
false
;
for
(
i
=
0
;
i
<
2
;
i
++
)
{
rdev
->
irq
.
crtc_vblank_int
[
i
]
=
false
;
rdev
->
irq
.
hpd
[
i
]
=
false
;
}
radeon_irq_set
(
rdev
);
}
...
...
@@ -128,17 +129,22 @@ int radeon_irq_kms_init(struct radeon_device *rdev)
DRM_INFO
(
"radeon: using MSI.
\n
"
);
}
}
drm_irq_install
(
rdev
->
ddev
);
rdev
->
irq
.
installed
=
true
;
r
=
drm_irq_install
(
rdev
->
ddev
);
if
(
r
)
{
rdev
->
irq
.
installed
=
false
;
return
r
;
}
DRM_INFO
(
"radeon: irq initialized.
\n
"
);
return
0
;
}
void
radeon_irq_kms_fini
(
struct
radeon_device
*
rdev
)
{
drm_vblank_cleanup
(
rdev
->
ddev
);
if
(
rdev
->
irq
.
installed
)
{
rdev
->
irq
.
installed
=
false
;
drm_irq_uninstall
(
rdev
->
ddev
);
rdev
->
irq
.
installed
=
false
;
if
(
rdev
->
msi_enabled
)
pci_disable_msi
(
rdev
->
pdev
);
}
...
...
drivers/gpu/drm/radeon/radeon_legacy_tv.c
View file @
e8d6d615
...
...
@@ -77,7 +77,7 @@ struct radeon_tv_mode_constants {
unsigned
pix_to_tv
;
};
static
const
uint16_t
hor_timing_NTSC
[]
=
{
static
const
uint16_t
hor_timing_NTSC
[
MAX_H_CODE_TIMING_LEN
]
=
{
0x0007
,
0x003f
,
0x0263
,
...
...
@@ -98,7 +98,7 @@ static const uint16_t hor_timing_NTSC[] = {
0
};
static
const
uint16_t
vert_timing_NTSC
[]
=
{
static
const
uint16_t
vert_timing_NTSC
[
MAX_V_CODE_TIMING_LEN
]
=
{
0x2001
,
0x200d
,
0x1006
,
...
...
@@ -115,7 +115,7 @@ static const uint16_t vert_timing_NTSC[] = {
0
};
static
const
uint16_t
hor_timing_PAL
[]
=
{
static
const
uint16_t
hor_timing_PAL
[
MAX_H_CODE_TIMING_LEN
]
=
{
0x0007
,
0x0058
,
0x027c
,
...
...
@@ -136,7 +136,7 @@ static const uint16_t hor_timing_PAL[] = {
0
};
static
const
uint16_t
vert_timing_PAL
[
]
=
{
static
const
uint16_t
vert_timing_PAL
[
MAX_V_CODE_TIMING_LEN
]
=
{
0x2001
,
0x200c
,
0x1005
,
...
...
@@ -623,9 +623,9 @@ void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
}
flicker_removal
=
(
tmp
+
500
)
/
1000
;
if
(
flicker_removal
<
3
)
flicker_removal
=
3
;
for
(
i
=
0
;
i
<
6
;
++
i
)
{
if
(
flicker_removal
<
2
)
flicker_removal
=
2
;
for
(
i
=
0
;
i
<
ARRAY_SIZE
(
SLOPE_limit
)
;
++
i
)
{
if
(
flicker_removal
==
SLOPE_limit
[
i
])
break
;
}
...
...
drivers/gpu/drm/radeon/radeon_mode.h
View file @
e8d6d615
...
...
@@ -46,32 +46,6 @@ struct radeon_device;
#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
#define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
enum
radeon_connector_type
{
CONNECTOR_NONE
,
CONNECTOR_VGA
,
CONNECTOR_DVI_I
,
CONNECTOR_DVI_D
,
CONNECTOR_DVI_A
,
CONNECTOR_STV
,
CONNECTOR_CTV
,
CONNECTOR_LVDS
,
CONNECTOR_DIGITAL
,
CONNECTOR_SCART
,
CONNECTOR_HDMI_TYPE_A
,
CONNECTOR_HDMI_TYPE_B
,
CONNECTOR_0XC
,
CONNECTOR_0XD
,
CONNECTOR_DIN
,
CONNECTOR_DISPLAY_PORT
,
CONNECTOR_UNSUPPORTED
};
enum
radeon_dvi_type
{
DVI_AUTO
,
DVI_DIGITAL
,
DVI_ANALOG
};
enum
radeon_rmx_type
{
RMX_OFF
,
RMX_FULL
,
...
...
drivers/gpu/drm/radeon/radeon_object.c
View file @
e8d6d615
...
...
@@ -221,8 +221,9 @@ int radeon_bo_unpin(struct radeon_bo *bo)
int
radeon_bo_evict_vram
(
struct
radeon_device
*
rdev
)
{
if
(
rdev
->
flags
&
RADEON_IS_IGP
)
{
/* Useless to evict on IGP chips */
return
0
;
if
(
rdev
->
mc
.
igp_sideport_enabled
==
false
)
/* Useless to evict on IGP chips */
return
0
;
}
return
ttm_bo_evict_mm
(
&
rdev
->
mman
.
bdev
,
TTM_PL_VRAM
);
}
...
...
drivers/gpu/drm/radeon/rs400.c
View file @
e8d6d615
...
...
@@ -356,6 +356,7 @@ static int rs400_mc_init(struct radeon_device *rdev)
rdev
->
mc
.
vram_location
=
G_00015C_MC_FB_START
(
tmp
)
<<
16
;
rdev
->
mc
.
gtt_location
=
0xFFFFFFFFUL
;
r
=
radeon_mc_setup
(
rdev
);
rdev
->
mc
.
igp_sideport_enabled
=
radeon_combios_sideport_present
(
rdev
);
if
(
r
)
return
r
;
return
0
;
...
...
@@ -395,6 +396,7 @@ static int rs400_startup(struct radeon_device *rdev)
return
r
;
/* Enable IRQ */
r100_irq_set
(
rdev
);
rdev
->
config
.
r300
.
hdp_cntl
=
RREG32
(
RADEON_HOST_PATH_CNTL
);
/* 1M ring buffer */
r
=
r100_cp_init
(
rdev
,
1024
*
1024
);
if
(
r
)
{
...
...
drivers/gpu/drm/radeon/rs600.c
View file @
e8d6d615
...
...
@@ -56,6 +56,7 @@ int rs600_mc_init(struct radeon_device *rdev)
rdev
->
mc
.
vram_location
=
G_000004_MC_FB_START
(
tmp
)
<<
16
;
rdev
->
mc
.
gtt_location
=
0xffffffffUL
;
r
=
radeon_mc_setup
(
rdev
);
rdev
->
mc
.
igp_sideport_enabled
=
radeon_atombios_sideport_present
(
rdev
);
if
(
r
)
return
r
;
return
0
;
...
...
@@ -134,7 +135,8 @@ void rs600_hpd_init(struct radeon_device *rdev)
break
;
}
}
rs600_irq_set
(
rdev
);
if
(
rdev
->
irq
.
installed
)
rs600_irq_set
(
rdev
);
}
void
rs600_hpd_fini
(
struct
radeon_device
*
rdev
)
...
...
@@ -315,6 +317,11 @@ int rs600_irq_set(struct radeon_device *rdev)
u32
hpd2
=
RREG32
(
R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL
)
&
~
S_007D18_DC_HOT_PLUG_DETECT2_INT_EN
(
1
);
if
(
!
rdev
->
irq
.
installed
)
{
WARN
(
1
,
"Can't enable IRQ/MSI because no handler is installed.
\n
"
);
WREG32
(
R_000040_GEN_INT_CNTL
,
0
);
return
-
EINVAL
;
}
if
(
rdev
->
irq
.
sw_int
)
{
tmp
|=
S_000040_SW_INT_EN
(
1
);
}
...
...
@@ -553,6 +560,7 @@ static int rs600_startup(struct radeon_device *rdev)
return
r
;
/* Enable IRQ */
rs600_irq_set
(
rdev
);
rdev
->
config
.
r300
.
hdp_cntl
=
RREG32
(
RADEON_HOST_PATH_CNTL
);
/* 1M ring buffer */
r
=
r100_cp_init
(
rdev
,
1024
*
1024
);
if
(
r
)
{
...
...
drivers/gpu/drm/radeon/rs690.c
View file @
e8d6d615
...
...
@@ -172,6 +172,7 @@ static int rs690_mc_init(struct radeon_device *rdev)
rdev
->
mc
.
vram_location
=
G_000100_MC_FB_START
(
tmp
)
<<
16
;
rdev
->
mc
.
gtt_location
=
0xFFFFFFFFUL
;
r
=
radeon_mc_setup
(
rdev
);
rdev
->
mc
.
igp_sideport_enabled
=
radeon_atombios_sideport_present
(
rdev
);
if
(
r
)
return
r
;
return
0
;
...
...
@@ -625,6 +626,7 @@ static int rs690_startup(struct radeon_device *rdev)
return
r
;
/* Enable IRQ */
rs600_irq_set
(
rdev
);
rdev
->
config
.
r300
.
hdp_cntl
=
RREG32
(
RADEON_HOST_PATH_CNTL
);
/* 1M ring buffer */
r
=
r100_cp_init
(
rdev
,
1024
*
1024
);
if
(
r
)
{
...
...
drivers/gpu/drm/radeon/rv515.c
View file @
e8d6d615
...
...
@@ -479,6 +479,7 @@ static int rv515_startup(struct radeon_device *rdev)
}
/* Enable IRQ */
rs600_irq_set
(
rdev
);
rdev
->
config
.
r300
.
hdp_cntl
=
RREG32
(
RADEON_HOST_PATH_CNTL
);
/* 1M ring buffer */
r
=
r100_cp_init
(
rdev
,
1024
*
1024
);
if
(
r
)
{
...
...
drivers/gpu/drm/radeon/rv770.c
View file @
e8d6d615
...
...
@@ -1096,8 +1096,7 @@ void rv770_fini(struct radeon_device *rdev)
radeon_gem_fini
(
rdev
);
radeon_fence_driver_fini
(
rdev
);
radeon_clocks_fini
(
rdev
);
if
(
rdev
->
flags
&
RADEON_IS_AGP
)
radeon_agp_fini
(
rdev
);
radeon_agp_fini
(
rdev
);
radeon_bo_fini
(
rdev
);
radeon_atombios_fini
(
rdev
);
kfree
(
rdev
->
bios
);
...
...
include/drm/drm_mode.h
View file @
e8d6d615
...
...
@@ -160,6 +160,7 @@ struct drm_mode_get_encoder {
#define DRM_MODE_CONNECTOR_HDMIA 11
#define DRM_MODE_CONNECTOR_HDMIB 12
#define DRM_MODE_CONNECTOR_TV 13
#define DRM_MODE_CONNECTOR_eDP 14
struct
drm_mode_get_connector
{
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment