Commit e98fd32c authored by Jeff Garzik's avatar Jeff Garzik

Merge redhat.com:/spare/repo/linux-2.5

into redhat.com:/spare/repo/libata-2.5
parents 3940ed85 3c56486b
...@@ -34,11 +34,16 @@ ...@@ -34,11 +34,16 @@
#include "hosts.h" #include "hosts.h"
#include <linux/libata.h> #include <linux/libata.h>
#define DRV_NAME "ata_sil" #define DRV_NAME "sata_sil"
#define DRV_VERSION "0.51" #define DRV_VERSION "0.52"
enum { enum {
sil_3112 = 0, sil_3112 = 0,
sil_3114 = 1,
SIL_SYSCFG = 0x48,
SIL_MASK_IDE0_INT = (1 << 22),
SIL_MASK_IDE1_INT = (1 << 23),
SIL_IDE0_TF = 0x80, SIL_IDE0_TF = 0x80,
SIL_IDE0_CTL = 0x8A, SIL_IDE0_CTL = 0x8A,
...@@ -49,6 +54,19 @@ enum { ...@@ -49,6 +54,19 @@ enum {
SIL_IDE1_CTL = 0xCA, SIL_IDE1_CTL = 0xCA,
SIL_IDE1_BMDMA = 0x08, SIL_IDE1_BMDMA = 0x08,
SIL_IDE1_SCR = 0x180, SIL_IDE1_SCR = 0x180,
SIL_IDE2_TF = 0x280,
SIL_IDE2_CTL = 0x28A,
SIL_IDE2_BMDMA = 0x200,
SIL_IDE2_SCR = 0x300,
SIL_IDE3_TF = 0x2C0,
SIL_IDE3_CTL = 0x2CA,
SIL_IDE3_BMDMA = 0x208,
SIL_IDE3_SCR = 0x380,
SIL_QUIRK_MOD15WRITE = (1 << 0),
SIL_QUIRK_UDMA5MAX = (1 << 1),
}; };
static void sil_set_piomode (struct ata_port *ap, struct ata_device *adev, static void sil_set_piomode (struct ata_port *ap, struct ata_device *adev,
...@@ -62,9 +80,33 @@ static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); ...@@ -62,9 +80,33 @@ static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
static struct pci_device_id sil_pci_tbl[] = { static struct pci_device_id sil_pci_tbl[] = {
{ 0x1095, 0x3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 }, { 0x1095, 0x3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
{ 0x1095, 0x0240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
{ 0x1095, 0x3512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
{ 0x1095, 0x3114, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3114 },
{ } /* terminate list */ { } /* terminate list */
}; };
/* TODO firmware versions should be added - eric */
struct sil_drivelist {
const char * product;
unsigned int quirk;
} sil_blacklist [] = {
{ "ST320012AS", SIL_QUIRK_MOD15WRITE },
{ "ST330013AS", SIL_QUIRK_MOD15WRITE },
{ "ST340017AS", SIL_QUIRK_MOD15WRITE },
{ "ST360015AS", SIL_QUIRK_MOD15WRITE },
{ "ST380023AS", SIL_QUIRK_MOD15WRITE },
{ "ST3120023AS", SIL_QUIRK_MOD15WRITE },
{ "ST340014ASL", SIL_QUIRK_MOD15WRITE },
{ "ST360014ASL", SIL_QUIRK_MOD15WRITE },
{ "ST380011ASL", SIL_QUIRK_MOD15WRITE },
{ "ST3120022ASL", SIL_QUIRK_MOD15WRITE },
{ "ST3160021ASL", SIL_QUIRK_MOD15WRITE },
{ "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX },
{ }
};
static struct pci_driver sil_pci_driver = { static struct pci_driver sil_pci_driver = {
.name = DRV_NAME, .name = DRV_NAME,
.id_table = sil_pci_tbl, .id_table = sil_pci_tbl,
...@@ -113,6 +155,14 @@ static struct ata_port_operations sil_ops = { ...@@ -113,6 +155,14 @@ static struct ata_port_operations sil_ops = {
static struct ata_port_info sil_port_info[] = { static struct ata_port_info sil_port_info[] = {
/* sil_3112 */ /* sil_3112 */
{
.sht = &sil_sht,
.host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
ATA_FLAG_SRST | ATA_FLAG_MMIO,
.pio_mask = 0x03, /* pio3-4 */
.udma_mask = 0x7f, /* udma0-6; FIXME */
.port_ops = &sil_ops,
}, /* sil_3114 */
{ {
.sht = &sil_sht, .sht = &sil_sht,
.host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
...@@ -182,34 +232,52 @@ static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val) ...@@ -182,34 +232,52 @@ static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
* information on these errata, I will create a more exhaustive * information on these errata, I will create a more exhaustive
* list, and apply the fixups to only the specific * list, and apply the fixups to only the specific
* devices/hosts/firmwares that need it. * devices/hosts/firmwares that need it.
*
* 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
* The Maxtor quirk is in the blacklist, but I'm keeping the original
* pessimistic fix for the following reasons:
* - There seems to be less info on it, only one device gleaned off the
* Windows driver, maybe only one is affected. More info would be greatly
* appreciated.
* - But then again UDMA5 is hardly anything to complain about
*/ */
static void sil_dev_config(struct ata_port *ap, struct ata_device *dev) static void sil_dev_config(struct ata_port *ap, struct ata_device *dev)
{ {
unsigned int n, quirks = 0;
u32 class_rev = 0;
const char *s = &dev->product[0]; const char *s = &dev->product[0];
unsigned int len = strnlen(s, sizeof(dev->product)); unsigned int len = strnlen(s, sizeof(dev->product));
pci_read_config_dword(ap->host_set->pdev, PCI_CLASS_REVISION, &class_rev);
class_rev &= 0xff;
/* ATAPI specifies that empty space is blank-filled; remove blanks */ /* ATAPI specifies that empty space is blank-filled; remove blanks */
while ((len > 0) && (s[len - 1] == ' ')) while ((len > 0) && (s[len - 1] == ' '))
len--; len--;
/* limit to udma5 */ for (n = 0; sil_blacklist[n].product; n++)
if (!memcmp(s, "Maxtor ", 7)) { if (!memcmp(sil_blacklist[n].product, s,
printk(KERN_INFO "ata%u(%u): applying pessimistic Maxtor errata fix\n", strlen(sil_blacklist[n].product))) {
quirks = sil_blacklist[n].quirk;
break;
}
/* limit requests to 15 sectors */
if ((class_rev <= 0x01) && (quirks & SIL_QUIRK_MOD15WRITE)) {
printk(KERN_INFO "ata%u(%u): applying Seagate errata fix\n",
ap->id, dev->devno); ap->id, dev->devno);
ap->udma_mask &= ATA_UDMA5; ap->host->max_sectors = 15;
ap->host->hostt->max_sectors = 15;
return; return;
} }
/* limit requests to 15 sectors */ /* limit to udma5 */
if ((len > 4) && (!memcmp(s, "ST", 2))) { /* is this for (class_rev <= 0x01) only, too? */
if ((!memcmp(s + len - 2, "AS", 2)) || if (quirks & SIL_QUIRK_UDMA5MAX) {
(!memcmp(s + len - 3, "ASL", 3))) { printk(KERN_INFO "ata%u(%u): applying Maxtor errata fix %s\n",
printk(KERN_INFO "ata%u(%u): applying pessimistic Seagate errata fix\n", ap->id, dev->devno, s);
ap->id, dev->devno); ap->udma_mask &= ATA_UDMA5;
ap->host->max_sectors = 15; return;
ap->host->hostt->max_sectors = 15;
return;
}
} }
} }
...@@ -236,6 +304,7 @@ static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) ...@@ -236,6 +304,7 @@ static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
unsigned long base; unsigned long base;
void *mmio_base; void *mmio_base;
int rc; int rc;
u32 tmp;
if (!printed_version++) if (!printed_version++)
printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n"); printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
...@@ -267,7 +336,7 @@ static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) ...@@ -267,7 +336,7 @@ static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
probe_ent->pdev = pdev; probe_ent->pdev = pdev;
probe_ent->port_ops = sil_port_info[ent->driver_data].port_ops; probe_ent->port_ops = sil_port_info[ent->driver_data].port_ops;
probe_ent->sht = sil_port_info[ent->driver_data].sht; probe_ent->sht = sil_port_info[ent->driver_data].sht;
probe_ent->n_ports = 2; probe_ent->n_ports = (ent->driver_data == sil_3114) ? 4 : 2;
probe_ent->pio_mask = sil_port_info[ent->driver_data].pio_mask; probe_ent->pio_mask = sil_port_info[ent->driver_data].pio_mask;
probe_ent->udma_mask = sil_port_info[ent->driver_data].udma_mask; probe_ent->udma_mask = sil_port_info[ent->driver_data].udma_mask;
probe_ent->irq = pdev->irq; probe_ent->irq = pdev->irq;
...@@ -296,6 +365,28 @@ static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) ...@@ -296,6 +365,28 @@ static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
probe_ent->port[1].scr_addr = base + SIL_IDE1_SCR; probe_ent->port[1].scr_addr = base + SIL_IDE1_SCR;
ata_std_ports(&probe_ent->port[1]); ata_std_ports(&probe_ent->port[1]);
/* make sure IDE0/1 interrupts are not masked */
tmp = readl(mmio_base + SIL_SYSCFG);
if (tmp & (SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT)) {
tmp &= ~(SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT);
writel(tmp, mmio_base + SIL_SYSCFG);
readl(mmio_base + SIL_SYSCFG); /* flush */
}
if (ent->driver_data == sil_3114) {
probe_ent->port[2].cmd_addr = base + SIL_IDE2_TF;
probe_ent->port[2].ctl_addr = base + SIL_IDE2_CTL;
probe_ent->port[2].bmdma_addr = base + SIL_IDE2_BMDMA;
probe_ent->port[2].scr_addr = base + SIL_IDE2_SCR;
ata_std_ports(&probe_ent->port[2]);
probe_ent->port[3].cmd_addr = base + SIL_IDE3_TF;
probe_ent->port[3].ctl_addr = base + SIL_IDE3_CTL;
probe_ent->port[3].bmdma_addr = base + SIL_IDE3_BMDMA;
probe_ent->port[3].scr_addr = base + SIL_IDE3_SCR;
ata_std_ports(&probe_ent->port[3]);
}
pci_set_master(pdev); pci_set_master(pdev);
/* FIXME: check ata_device_add return value */ /* FIXME: check ata_device_add return value */
......
...@@ -38,13 +38,41 @@ ...@@ -38,13 +38,41 @@
#include "hosts.h" #include "hosts.h"
#include <linux/libata.h> #include <linux/libata.h>
#ifdef CONFIG_ALL_PPC #ifdef CONFIG_PPC_OF
#include <asm/prom.h> #include <asm/prom.h>
#include <asm/pci-bridge.h> #include <asm/pci-bridge.h>
#endif /* CONFIG_ALL_PPC */ #endif /* CONFIG_PPC_OF */
#define DRV_NAME "ata_k2" #define DRV_NAME "sata_svw"
#define DRV_VERSION "1.03" #define DRV_VERSION "1.04"
/* Taskfile registers offsets */
#define K2_SATA_TF_CMD_OFFSET 0x00
#define K2_SATA_TF_DATA_OFFSET 0x00
#define K2_SATA_TF_ERROR_OFFSET 0x04
#define K2_SATA_TF_NSECT_OFFSET 0x08
#define K2_SATA_TF_LBAL_OFFSET 0x0c
#define K2_SATA_TF_LBAM_OFFSET 0x10
#define K2_SATA_TF_LBAH_OFFSET 0x14
#define K2_SATA_TF_DEVICE_OFFSET 0x18
#define K2_SATA_TF_CMDSTAT_OFFSET 0x1c
#define K2_SATA_TF_CTL_OFFSET 0x20
/* DMA base */
#define K2_SATA_DMA_CMD_OFFSET 0x30
/* SCRs base */
#define K2_SATA_SCR_STATUS_OFFSET 0x40
#define K2_SATA_SCR_ERROR_OFFSET 0x44
#define K2_SATA_SCR_CONTROL_OFFSET 0x48
/* Others */
#define K2_SATA_SICR1_OFFSET 0x80
#define K2_SATA_SICR2_OFFSET 0x84
#define K2_SATA_SIM_OFFSET 0x88
/* Port stride */
#define K2_SATA_PORT_OFFSET 0x100
static u32 k2_sata_scr_read (struct ata_port *ap, unsigned int sc_reg) static u32 k2_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
...@@ -139,7 +167,7 @@ static void k2_sata_set_udmamode (struct ata_port *ap, struct ata_device *adev, ...@@ -139,7 +167,7 @@ static void k2_sata_set_udmamode (struct ata_port *ap, struct ata_device *adev,
} }
#ifdef CONFIG_ALL_PPC #ifdef CONFIG_PPC_OF
/* /*
* k2_sata_proc_info * k2_sata_proc_info
* inout : decides on the direction of the dataflow and the meaning of the * inout : decides on the direction of the dataflow and the meaning of the
...@@ -151,29 +179,15 @@ static void k2_sata_set_udmamode (struct ata_port *ap, struct ata_device *adev, ...@@ -151,29 +179,15 @@ static void k2_sata_set_udmamode (struct ata_port *ap, struct ata_device *adev,
* length: If inout==FALSE max number of bytes to be written into the buffer * length: If inout==FALSE max number of bytes to be written into the buffer
* else number of bytes in the buffer * else number of bytes in the buffer
*/ */
static int k2_sata_proc_info(char *page, char **start, off_t offset, int count, static int k2_sata_proc_info(struct Scsi_Host *shost, char *page, char **start,
int hostno, int inout) off_t offset, int count, int inout)
{ {
struct Scsi_Host *hpnt;
struct ata_port *ap; struct ata_port *ap;
struct device_node *np; struct device_node *np;
int len, index; int len, index;
/* Find ourself. That's locking-broken, shitty etc... but thanks to
* /proc/scsi interface and lack of state kept around in this driver,
* its best I want to do for now...
*/
hpnt = scsi_hostlist;
while (hpnt) {
if (hostno == hpnt->host_no)
break;
hpnt = hpnt->next;
}
if (!hpnt)
return 0;
/* Find the ata_port */ /* Find the ata_port */
ap = (struct ata_port *) &hpnt->hostdata[0]; ap = (struct ata_port *) &shost->hostdata[0];
if (ap == NULL) if (ap == NULL)
return 0; return 0;
...@@ -198,7 +212,7 @@ static int k2_sata_proc_info(char *page, char **start, off_t offset, int count, ...@@ -198,7 +212,7 @@ static int k2_sata_proc_info(char *page, char **start, off_t offset, int count,
return len; return len;
} }
#endif /* CONFIG_ALL_PPC */ #endif /* CONFIG_PPC_OF */
static Scsi_Host_Template k2_sata_sht = { static Scsi_Host_Template k2_sata_sht = {
...@@ -216,8 +230,8 @@ static Scsi_Host_Template k2_sata_sht = { ...@@ -216,8 +230,8 @@ static Scsi_Host_Template k2_sata_sht = {
.proc_name = DRV_NAME, .proc_name = DRV_NAME,
.dma_boundary = ATA_DMA_BOUNDARY, .dma_boundary = ATA_DMA_BOUNDARY,
.slave_configure = ata_scsi_slave_config, .slave_configure = ata_scsi_slave_config,
#ifdef CONFIG_ALL_PPC #ifdef CONFIG_PPC_OF
.proc_info = k2_sata_proc_info .proc_info = k2_sata_proc_info,
#endif #endif
.bios_param = ata_std_bios_param, .bios_param = ata_std_bios_param,
}; };
...@@ -243,21 +257,20 @@ static struct ata_port_operations k2_sata_ops = { ...@@ -243,21 +257,20 @@ static struct ata_port_operations k2_sata_ops = {
.port_stop = ata_port_stop, .port_stop = ata_port_stop,
}; };
static void k2_sata_setup_port(struct ata_ioports *port, unsigned long base) static void k2_sata_setup_port(struct ata_ioports *port, unsigned long base)
{ {
port->cmd_addr = base; port->cmd_addr = base + K2_SATA_TF_CMD_OFFSET;
port->data_addr = base; port->data_addr = base + K2_SATA_TF_DATA_OFFSET;
port->error_addr = base + 0x4; port->error_addr = base + K2_SATA_TF_ERROR_OFFSET;
port->nsect_addr = base + 0x8; port->nsect_addr = base + K2_SATA_TF_NSECT_OFFSET;
port->lbal_addr = base + 0xc; port->lbal_addr = base + K2_SATA_TF_LBAL_OFFSET;
port->lbam_addr = base + 0x10; port->lbam_addr = base + K2_SATA_TF_LBAM_OFFSET;
port->lbah_addr = base + 0x14; port->lbah_addr = base + K2_SATA_TF_LBAH_OFFSET;
port->device_addr = base + 0x18; port->device_addr = base + K2_SATA_TF_DEVICE_OFFSET;
port->cmdstat_addr = base + 0x1c; port->cmdstat_addr = base + K2_SATA_TF_CMDSTAT_OFFSET;
port->ctl_addr = base + 0x20; port->ctl_addr = base + K2_SATA_TF_CTL_OFFSET;
port->bmdma_addr = base + 0x30; port->bmdma_addr = base + K2_SATA_DMA_CMD_OFFSET;
port->scr_addr = base + 0x40; port->scr_addr = base + K2_SATA_SCR_STATUS_OFFSET;
} }
...@@ -279,7 +292,14 @@ static int k2_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *e ...@@ -279,7 +292,14 @@ static int k2_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *e
rc = pci_enable_device(pdev); rc = pci_enable_device(pdev);
if (rc) if (rc)
return rc; return rc;
/*
* Check if we have resources mapped at all (second function may
* have been disabled by firmware)
*/
if (pci_resource_len(pdev, 5) == 0)
return -ENODEV;
/* Request PCI regions */
rc = pci_request_regions(pdev, DRV_NAME); rc = pci_request_regions(pdev, DRV_NAME);
if (rc) if (rc)
goto err_out; goto err_out;
...@@ -306,44 +326,37 @@ static int k2_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *e ...@@ -306,44 +326,37 @@ static int k2_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *e
} }
base = (unsigned long) mmio_base; base = (unsigned long) mmio_base;
/*
* Check for the "disabled" second function to avoid registering
* useless interfaces on K2
*/
if (readl(mmio_base + 0x40) == 0xffffffffUL &&
readl(mmio_base + 0x140) == 0xffffffffUL) {
rc = -ENODEV;
goto err_out_unmap;
}
/* Clear a magic bit in SCR1 according to Darwin, those help /* Clear a magic bit in SCR1 according to Darwin, those help
* some funky seagate drives (though so far, those were already * some funky seagate drives (though so far, those were already
* set by the firmware on the machines I had access to * set by the firmware on the machines I had access to
*/ */
writel(readl(mmio_base + 0x80) & ~0x00040000, mmio_base + 0x80); writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000,
mmio_base + K2_SATA_SICR1_OFFSET);
/* Clear SATA error & interrupts we don't use */ /* Clear SATA error & interrupts we don't use */
writel(0xffffffff, mmio_base + 0x44); writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET);
writel(0x0, mmio_base + 0x88); writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);
probe_ent->sht = &k2_sata_sht; probe_ent->sht = &k2_sata_sht;
probe_ent->host_flags = ATA_FLAG_SATA | ATA_FLAG_SATA_RESET | probe_ent->host_flags = ATA_FLAG_SATA | ATA_FLAG_SATA_RESET |
ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO; ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO;
probe_ent->port_ops = &k2_sata_ops; probe_ent->port_ops = &k2_sata_ops;
probe_ent->n_ports = 2; probe_ent->n_ports = 4;
probe_ent->irq = pdev->irq; probe_ent->irq = pdev->irq;
probe_ent->irq_flags = SA_SHIRQ; probe_ent->irq_flags = SA_SHIRQ;
probe_ent->mmio_base = mmio_base; probe_ent->mmio_base = mmio_base;
/* /* We don't care much about the PIO/UDMA masks, but the core won't like us
* We don't care much about the PIO/UDMA masks, but the core won't like us
* if we don't fill these * if we don't fill these
*/ */
probe_ent->pio_mask = 0x1f; probe_ent->pio_mask = 0x1f;
probe_ent->udma_mask = 0x7f; probe_ent->udma_mask = 0x3f;
k2_sata_setup_port(&probe_ent->port[0], base); /* We have 4 ports per PCI function */
k2_sata_setup_port(&probe_ent->port[1], base + 0x100); k2_sata_setup_port(&probe_ent->port[0], base + 0 * K2_SATA_PORT_OFFSET);
k2_sata_setup_port(&probe_ent->port[1], base + 1 * K2_SATA_PORT_OFFSET);
k2_sata_setup_port(&probe_ent->port[2], base + 2 * K2_SATA_PORT_OFFSET);
k2_sata_setup_port(&probe_ent->port[3], base + 3 * K2_SATA_PORT_OFFSET);
pci_set_master(pdev); pci_set_master(pdev);
...@@ -353,8 +366,6 @@ static int k2_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *e ...@@ -353,8 +366,6 @@ static int k2_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *e
return 0; return 0;
err_out_unmap:
iounmap((void *)base);
err_out_free_ent: err_out_free_ent:
kfree(probe_ent); kfree(probe_ent);
err_out_regions: err_out_regions:
......
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