Commit e9de688d authored by Andrew Bresticker's avatar Andrew Bresticker Committed by Ralf Baechle

irqchip: mips-gic: Support local interrupts

The MIPS GIC supports 7 local interrupts, 2 of which are the GIC
local watchdog and count/compare timer.  The remainder are CPU
interrupts which may optionally be re-routed through the GIC.
GIC hardware IRQs 0-6 are now used for local interrupts while
hardware IRQs 7+ are used for external (shared) interrupts.

Note that the 5 CPU interrupts may not be re-routable through
the GIC.  In that case mapping will fail and the vectors reported
in C0_IntCtl should be used instead.  gic_get_c0_compare_int() and
gic_get_c0_perfcount_int() will return the correct IRQ number to
use for the C0 timer and perfcounter interrupts based on the
routability of those interrupts through the GIC.

A separate irq_chip, with callbacks that mask/unmask the local
interrupt on all CPUs, is used for the C0 timer and performance
counter interrupts since all other platforms do not use the percpu
IRQ API for those interrupts.

Malta, SEAD-3, and the GIC clockevent driver have been updated
to use local interrupts and the R4K clockevent driver has been
updated to poll for C0 timer interrupts through the GIC when
the GIC is present.
Signed-off-by: default avatarAndrew Bresticker <abrestic@chromium.org>
Acked-by: default avatarJason Cooper <jason@lakedaemon.net>
Reviewed-by: default avatarQais Yousef <qais.yousef@imgtec.com>
Tested-by: default avatarQais Yousef <qais.yousef@imgtec.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jeffrey Deans <jeffrey.deans@imgtec.com>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Jonas Gorski <jogo@openwrt.org>
Cc: John Crispin <blogic@openwrt.org>
Cc: David Daney <ddaney.cavm@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/7819/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 4a6a3ea3
...@@ -209,6 +209,7 @@ ...@@ -209,6 +209,7 @@
#define GIC_VPE_WD_MAP_OFS 0x0040 #define GIC_VPE_WD_MAP_OFS 0x0040
#define GIC_VPE_COMPARE_MAP_OFS 0x0044 #define GIC_VPE_COMPARE_MAP_OFS 0x0044
#define GIC_VPE_TIMER_MAP_OFS 0x0048 #define GIC_VPE_TIMER_MAP_OFS 0x0048
#define GIC_VPE_FDC_MAP_OFS 0x004c
#define GIC_VPE_PERFCTR_MAP_OFS 0x0050 #define GIC_VPE_PERFCTR_MAP_OFS 0x0050
#define GIC_VPE_SWINT0_MAP_OFS 0x0054 #define GIC_VPE_SWINT0_MAP_OFS 0x0054
#define GIC_VPE_SWINT1_MAP_OFS 0x0058 #define GIC_VPE_SWINT1_MAP_OFS 0x0058
...@@ -262,6 +263,10 @@ ...@@ -262,6 +263,10 @@
#define GIC_MAP_MSK (MSK(6) << GIC_MAP_SHF) #define GIC_MAP_MSK (MSK(6) << GIC_MAP_SHF)
/* GIC_VPE_CTL Masks */ /* GIC_VPE_CTL Masks */
#define GIC_VPE_CTL_FDC_RTBL_SHF 4
#define GIC_VPE_CTL_FDC_RTBL_MSK (MSK(1) << GIC_VPE_CTL_FDC_RTBL_SHF)
#define GIC_VPE_CTL_SWINT_RTBL_SHF 3
#define GIC_VPE_CTL_SWINT_RTBL_MSK (MSK(1) << GIC_VPE_CTL_SWINT_RTBL_SHF)
#define GIC_VPE_CTL_PERFCNT_RTBL_SHF 2 #define GIC_VPE_CTL_PERFCNT_RTBL_SHF 2
#define GIC_VPE_CTL_PERFCNT_RTBL_MSK (MSK(1) << GIC_VPE_CTL_PERFCNT_RTBL_SHF) #define GIC_VPE_CTL_PERFCNT_RTBL_MSK (MSK(1) << GIC_VPE_CTL_PERFCNT_RTBL_SHF)
#define GIC_VPE_CTL_TIMER_RTBL_SHF 1 #define GIC_VPE_CTL_TIMER_RTBL_SHF 1
...@@ -329,16 +334,30 @@ ...@@ -329,16 +334,30 @@
/* Add 2 to convert GIC CPU pin to core interrupt */ /* Add 2 to convert GIC CPU pin to core interrupt */
#define GIC_CPU_PIN_OFFSET 2 #define GIC_CPU_PIN_OFFSET 2
/* Local GIC interrupts. */
#define GIC_INT_TMR (GIC_CPU_INT5)
#define GIC_INT_PERFCTR (GIC_CPU_INT5)
/* Add 2 to convert non-EIC hardware interrupt to EIC vector number. */ /* Add 2 to convert non-EIC hardware interrupt to EIC vector number. */
#define GIC_CPU_TO_VEC_OFFSET (2) #define GIC_CPU_TO_VEC_OFFSET (2)
/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */ /* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
#define GIC_PIN_TO_VEC_OFFSET (1) #define GIC_PIN_TO_VEC_OFFSET (1)
/* Local GIC interrupts. */
#define GIC_LOCAL_INT_WD 0 /* GIC watchdog */
#define GIC_LOCAL_INT_COMPARE 1 /* GIC count and compare timer */
#define GIC_LOCAL_INT_TIMER 2 /* CPU timer interrupt */
#define GIC_LOCAL_INT_PERFCTR 3 /* CPU performance counter */
#define GIC_LOCAL_INT_SWINT0 4 /* CPU software interrupt 0 */
#define GIC_LOCAL_INT_SWINT1 5 /* CPU software interrupt 1 */
#define GIC_LOCAL_INT_FDC 6 /* CPU fast debug channel */
#define GIC_NUM_LOCAL_INTRS 7
/* Convert between local/shared IRQ number and GIC HW IRQ number. */
#define GIC_LOCAL_HWIRQ_BASE 0
#define GIC_LOCAL_TO_HWIRQ(x) (GIC_LOCAL_HWIRQ_BASE + (x))
#define GIC_HWIRQ_TO_LOCAL(x) ((x) - GIC_LOCAL_HWIRQ_BASE)
#define GIC_SHARED_HWIRQ_BASE GIC_NUM_LOCAL_INTRS
#define GIC_SHARED_TO_HWIRQ(x) (GIC_SHARED_HWIRQ_BASE + (x))
#define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE)
#include <linux/clocksource.h> #include <linux/clocksource.h>
#include <linux/irq.h> #include <linux/irq.h>
...@@ -363,4 +382,6 @@ extern void gic_bind_eic_interrupt(int irq, int set); ...@@ -363,4 +382,6 @@ extern void gic_bind_eic_interrupt(int irq, int set);
extern unsigned int gic_get_timer_pending(void); extern unsigned int gic_get_timer_pending(void);
extern void gic_get_int_mask(unsigned long *dst, const unsigned long *src); extern void gic_get_int_mask(unsigned long *dst, const unsigned long *src);
extern unsigned int gic_get_int(void); extern unsigned int gic_get_int(void);
extern int gic_get_c0_compare_int(void);
extern int gic_get_c0_perfcount_int(void);
#endif /* _ASM_GICREGS_H */ #endif /* _ASM_GICREGS_H */
...@@ -10,6 +10,8 @@ ...@@ -10,6 +10,8 @@
#ifndef _MIPS_MALTAINT_H #ifndef _MIPS_MALTAINT_H
#define _MIPS_MALTAINT_H #define _MIPS_MALTAINT_H
#include <asm/gic.h>
/* /*
* Interrupts 0..15 are used for Malta ISA compatible interrupts * Interrupts 0..15 are used for Malta ISA compatible interrupts
*/ */
...@@ -61,6 +63,6 @@ ...@@ -61,6 +63,6 @@
#define MSC01E_INT_CPUCTR 11 #define MSC01E_INT_CPUCTR 11
/* GIC external interrupts */ /* GIC external interrupts */
#define GIC_INT_I8259A 3 #define GIC_INT_I8259A GIC_SHARED_TO_HWIRQ(3)
#endif /* !(_MIPS_MALTAINT_H) */ #endif /* !(_MIPS_MALTAINT_H) */
...@@ -10,6 +10,8 @@ ...@@ -10,6 +10,8 @@
#ifndef _MIPS_SEAD3INT_H #ifndef _MIPS_SEAD3INT_H
#define _MIPS_SEAD3INT_H #define _MIPS_SEAD3INT_H
#include <asm/gic.h>
/* SEAD-3 GIC address space definitions. */ /* SEAD-3 GIC address space definitions. */
#define GIC_BASE_ADDR 0x1b1c0000 #define GIC_BASE_ADDR 0x1b1c0000
#define GIC_ADDRSPACE_SZ (128 * 1024) #define GIC_ADDRSPACE_SZ (128 * 1024)
...@@ -22,9 +24,9 @@ ...@@ -22,9 +24,9 @@
#define CPU_INT_NET 6 #define CPU_INT_NET 6
/* GIC interrupt offsets */ /* GIC interrupt offsets */
#define GIC_INT_NET 0 #define GIC_INT_NET GIC_SHARED_TO_HWIRQ(0)
#define GIC_INT_UART1 2 #define GIC_INT_UART1 GIC_SHARED_TO_HWIRQ(2)
#define GIC_INT_UART0 3 #define GIC_INT_UART0 GIC_SHARED_TO_HWIRQ(3)
#define GIC_INT_EHCI 5 #define GIC_INT_EHCI GIC_SHARED_TO_HWIRQ(5)
#endif /* !(_MIPS_SEAD3INT_H) */ #endif /* !(_MIPS_SEAD3INT_H) */
...@@ -68,7 +68,7 @@ int gic_clockevent_init(void) ...@@ -68,7 +68,7 @@ int gic_clockevent_init(void)
if (!cpu_has_counter || !gic_frequency) if (!cpu_has_counter || !gic_frequency)
return -ENXIO; return -ENXIO;
irq = MIPS_GIC_IRQ_BASE; irq = MIPS_GIC_IRQ_BASE + GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_COMPARE);
cd = &per_cpu(gic_clockevent_device, cpu); cd = &per_cpu(gic_clockevent_device, cpu);
...@@ -91,16 +91,13 @@ int gic_clockevent_init(void) ...@@ -91,16 +91,13 @@ int gic_clockevent_init(void)
clockevents_register_device(cd); clockevents_register_device(cd);
GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_MAP), if (!gic_timer_irq_installed) {
GIC_MAP_TO_PIN_MSK | gic_cpu_pin); setup_percpu_irq(irq, &gic_compare_irqaction);
GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_SMASK), GIC_VPE_SMASK_CMP_MSK); gic_timer_irq_installed = 1;
}
if (gic_timer_irq_installed) enable_percpu_irq(irq, IRQ_TYPE_NONE);
return 0;
gic_timer_irq_installed = 1;
setup_irq(irq, &gic_compare_irqaction);
irq_set_handler(irq, handle_percpu_irq);
return 0; return 0;
} }
...@@ -86,7 +86,7 @@ void mips_event_handler(struct clock_event_device *dev) ...@@ -86,7 +86,7 @@ void mips_event_handler(struct clock_event_device *dev)
static int c0_compare_int_pending(void) static int c0_compare_int_pending(void)
{ {
#ifdef CONFIG_MIPS_GIC #ifdef CONFIG_MIPS_GIC
if (cpu_has_veic) if (gic_present)
return gic_get_timer_pending(); return gic_get_timer_pending();
#endif #endif
return (read_c0_cause() >> cp0_compare_irq_shift) & (1ul << CAUSEB_IP); return (read_c0_cause() >> cp0_compare_irq_shift) & (1ul << CAUSEB_IP);
......
...@@ -273,11 +273,7 @@ asmlinkage void plat_irq_dispatch(void) ...@@ -273,11 +273,7 @@ asmlinkage void plat_irq_dispatch(void)
irq = irq_ffs(pending); irq = irq_ffs(pending);
/* HACK: GIC doesn't properly dispatch local interrupts yet */ do_IRQ(MIPS_CPU_IRQ_BASE + irq);
if (gic_present && irq == MIPSCPU_INT_GIC && gic_compare_int())
do_IRQ(MIPS_GIC_IRQ_BASE);
else
do_IRQ(MIPS_CPU_IRQ_BASE + irq);
} }
#ifdef CONFIG_MIPS_MT_SMP #ifdef CONFIG_MIPS_MT_SMP
......
...@@ -126,9 +126,9 @@ int get_c0_perfcount_int(void) ...@@ -126,9 +126,9 @@ int get_c0_perfcount_int(void)
if (cpu_has_veic) { if (cpu_has_veic) {
set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch); set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch);
mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR; mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
} else if (gic_present) {
mips_cpu_perf_irq = gic_get_c0_perfcount_int();
} else if (cp0_perfcount_irq >= 0) { } else if (cp0_perfcount_irq >= 0) {
if (cpu_has_vint)
set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch);
mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
} else { } else {
mips_cpu_perf_irq = -1; mips_cpu_perf_irq = -1;
...@@ -139,15 +139,12 @@ int get_c0_perfcount_int(void) ...@@ -139,15 +139,12 @@ int get_c0_perfcount_int(void)
unsigned int get_c0_compare_int(void) unsigned int get_c0_compare_int(void)
{ {
#ifdef MSC01E_INT_BASE
if (cpu_has_veic) { if (cpu_has_veic) {
set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch); set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
} else } else if (gic_present) {
#endif mips_cpu_timer_irq = gic_get_c0_compare_int();
{ } else {
if (cpu_has_vint)
set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
} }
......
...@@ -8,24 +8,12 @@ ...@@ -8,24 +8,12 @@
#include <linux/init.h> #include <linux/init.h>
#include <asm/cpu.h> #include <asm/cpu.h>
#include <asm/gic.h>
#include <asm/setup.h> #include <asm/setup.h>
#include <asm/time.h> #include <asm/time.h>
#include <asm/irq.h> #include <asm/irq.h>
#include <asm/mips-boards/generic.h> #include <asm/mips-boards/generic.h>
static int mips_cpu_timer_irq;
static int mips_cpu_perf_irq;
static void mips_timer_dispatch(void)
{
do_IRQ(mips_cpu_timer_irq);
}
static void mips_perf_dispatch(void)
{
do_IRQ(mips_cpu_perf_irq);
}
static void __iomem *status_reg = (void __iomem *)0xbf000410; static void __iomem *status_reg = (void __iomem *)0xbf000410;
/* /*
...@@ -83,22 +71,18 @@ void read_persistent_clock(struct timespec *ts) ...@@ -83,22 +71,18 @@ void read_persistent_clock(struct timespec *ts)
int get_c0_perfcount_int(void) int get_c0_perfcount_int(void)
{ {
if (cp0_perfcount_irq >= 0) { if (gic_present)
if (cpu_has_vint) return gic_get_c0_compare_int();
set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch); if (cp0_perfcount_irq >= 0)
mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
} else { return -1;
mips_cpu_perf_irq = -1;
}
return mips_cpu_perf_irq;
} }
unsigned int get_c0_compare_int(void) unsigned int get_c0_compare_int(void)
{ {
if (cpu_has_vint) if (gic_present)
set_vi_handler(cp0_compare_irq, mips_timer_dispatch); return gic_get_c0_compare_int();
mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; return MIPS_CPU_IRQ_BASE + cp0_compare_irq;
return mips_cpu_timer_irq;
} }
void __init plat_time_init(void) void __init plat_time_init(void)
......
This diff is collapsed.
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment