Commit eaba5585 authored by Codrin Ciubotariu's avatar Codrin Ciubotariu Committed by Mark Brown

ASoC: codecs: ad193x: Use regmap_multi_reg_write() when initializing

Using regmap_multi_reg_write() when we set the default values for our
registers makes the code smaller and easier to read.
Suggested-by: default avatarTzung-Bi Shih <tzungbi@google.com>
Signed-off-by: default avatarCodrin Ciubotariu <codrin.ciubotariu@microchip.com>
Reviewed-by: default avatarTzung-Bi Shih <tzungbi@google.com>
Link: https://lore.kernel.org/r/20190710105119.22987-1-codrin.ciubotariu@microchip.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
parent f7408a3d
...@@ -413,15 +413,10 @@ static struct snd_soc_dai_driver ad193x_no_adc_dai = { ...@@ -413,15 +413,10 @@ static struct snd_soc_dai_driver ad193x_no_adc_dai = {
.ops = &ad193x_dai_ops, .ops = &ad193x_dai_ops,
}; };
struct ad193x_reg_default {
unsigned int reg;
unsigned int val;
};
/* codec register values to set after reset */ /* codec register values to set after reset */
static void ad193x_reg_default_init(struct ad193x_priv *ad193x) static void ad193x_reg_default_init(struct ad193x_priv *ad193x)
{ {
const struct ad193x_reg_default reg_init[] = { const struct reg_sequence reg_init[] = {
{ 0, 0x99 }, /* PLL_CLK_CTRL0: pll input: mclki/xi 12.288Mhz */ { 0, 0x99 }, /* PLL_CLK_CTRL0: pll input: mclki/xi 12.288Mhz */
{ 1, 0x04 }, /* PLL_CLK_CTRL1: no on-chip Vref */ { 1, 0x04 }, /* PLL_CLK_CTRL1: no on-chip Vref */
{ 2, 0x40 }, /* DAC_CTRL0: TDM mode */ { 2, 0x40 }, /* DAC_CTRL0: TDM mode */
...@@ -437,21 +432,17 @@ static void ad193x_reg_default_init(struct ad193x_priv *ad193x) ...@@ -437,21 +432,17 @@ static void ad193x_reg_default_init(struct ad193x_priv *ad193x)
{ 12, 0x00 }, /* DAC_L4_VOL: no attenuation */ { 12, 0x00 }, /* DAC_L4_VOL: no attenuation */
{ 13, 0x00 }, /* DAC_R4_VOL: no attenuation */ { 13, 0x00 }, /* DAC_R4_VOL: no attenuation */
}; };
const struct ad193x_reg_default reg_adc_init[] = { const struct reg_sequence reg_adc_init[] = {
{ 14, 0x03 }, /* ADC_CTRL0: high-pass filter enable */ { 14, 0x03 }, /* ADC_CTRL0: high-pass filter enable */
{ 15, 0x43 }, /* ADC_CTRL1: sata delay=1, adc aux mode */ { 15, 0x43 }, /* ADC_CTRL1: sata delay=1, adc aux mode */
{ 16, 0x00 }, /* ADC_CTRL2: reset */ { 16, 0x00 }, /* ADC_CTRL2: reset */
}; };
int i;
for (i = 0; i < ARRAY_SIZE(reg_init); i++) regmap_multi_reg_write(ad193x->regmap, reg_init, ARRAY_SIZE(reg_init));
regmap_write(ad193x->regmap, reg_init[i].reg, reg_init[i].val);
if (ad193x_has_adc(ad193x)) { if (ad193x_has_adc(ad193x)) {
for (i = 0; i < ARRAY_SIZE(reg_adc_init); i++) { regmap_multi_reg_write(ad193x->regmap, reg_adc_init,
regmap_write(ad193x->regmap, reg_adc_init[i].reg, ARRAY_SIZE(reg_adc_init));
reg_adc_init[i].val);
}
} }
} }
......
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