Commit ebd47c84 authored by Stephen Boyd's avatar Stephen Boyd

Merge branches 'clk-bulk-fix', 'clk-at91' and 'clk-sprd' into clk-next

 - Make clk_bulk_get_all() return an 'id' corresponding to clock-names

* clk-bulk-fix:
  clk: Make clk_bulk_get_all() return a valid "id"

* clk-at91:
  clk: at91: allow 24 Mhz clock as input for PLL
  clk: at91: select parent if main oscillator or bypass is enabled
  clk: at91: fix update bit maps on CFG_MOR write

* clk-sprd:
  clk: sprd: add missing kfree
......@@ -21,6 +21,10 @@
#define MOR_KEY_MASK (0xff << 16)
#define clk_main_parent_select(s) (((s) & \
(AT91_PMC_MOSCEN | \
AT91_PMC_OSCBYPASS)) ? 1 : 0)
struct clk_main_osc {
struct clk_hw hw;
struct regmap *regmap;
......@@ -113,7 +117,7 @@ static int clk_main_osc_is_prepared(struct clk_hw *hw)
regmap_read(regmap, AT91_PMC_SR, &status);
return (status & AT91_PMC_MOSCS) && (tmp & AT91_PMC_MOSCEN);
return (status & AT91_PMC_MOSCS) && clk_main_parent_select(tmp);
}
static const struct clk_ops main_osc_ops = {
......@@ -152,7 +156,7 @@ at91_clk_register_main_osc(struct regmap *regmap,
if (bypass)
regmap_update_bits(regmap,
AT91_CKGR_MOR, MOR_KEY_MASK |
AT91_PMC_MOSCEN,
AT91_PMC_OSCBYPASS,
AT91_PMC_OSCBYPASS | AT91_PMC_KEY);
hw = &osc->hw;
......@@ -450,7 +454,7 @@ static u8 clk_sam9x5_main_get_parent(struct clk_hw *hw)
regmap_read(clkmain->regmap, AT91_CKGR_MOR, &status);
return status & AT91_PMC_MOSCEN ? 1 : 0;
return clk_main_parent_select(status);
}
static const struct clk_ops sam9x5_main_ops = {
......@@ -492,7 +496,7 @@ at91_clk_register_sam9x5_main(struct regmap *regmap,
clkmain->hw.init = &init;
clkmain->regmap = regmap;
regmap_read(clkmain->regmap, AT91_CKGR_MOR, &status);
clkmain->parent = status & AT91_PMC_MOSCEN ? 1 : 0;
clkmain->parent = clk_main_parent_select(status);
hw = &clkmain->hw;
ret = clk_hw_register(NULL, &clkmain->hw);
......
......@@ -21,7 +21,7 @@ static const struct clk_range plla_outputs[] = {
};
static const struct clk_pll_characteristics plla_characteristics = {
.input = { .min = 12000000, .max = 12000000 },
.input = { .min = 12000000, .max = 24000000 },
.num_output = ARRAY_SIZE(plla_outputs),
.output = plla_outputs,
.icpll = plla_icpll,
......
......@@ -18,10 +18,13 @@ static int __must_check of_clk_bulk_get(struct device_node *np, int num_clks,
int ret;
int i;
for (i = 0; i < num_clks; i++)
for (i = 0; i < num_clks; i++) {
clks[i].id = NULL;
clks[i].clk = NULL;
}
for (i = 0; i < num_clks; i++) {
of_property_read_string_index(np, "clock-names", i, &clks[i].id);
clks[i].clk = of_clk_get(np, i);
if (IS_ERR(clks[i].clk)) {
ret = PTR_ERR(clks[i].clk);
......
......@@ -136,6 +136,7 @@ static unsigned long _sprd_pll_recalc_rate(const struct sprd_pll *pll,
k2 + refin * nint * CLK_PLL_1M;
}
kfree(cfg);
return rate;
}
......@@ -222,6 +223,7 @@ static int _sprd_pll_set_rate(const struct sprd_pll *pll,
if (!ret)
udelay(pll->udelay);
kfree(cfg);
return ret;
}
......
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