Commit ee360274 authored by Bai Ping's avatar Bai Ping Committed by Shawn Guo

clk: imx: Add clock support for imx6qp

most of the clock tree structures on i.MX6 Quad Plus are
same as on i.MX6Q. there still some differences between
these two SOCs. compared to the i.XM6Q, the differents of
clocks on i.MX6QP is mainly on:

1. New clock gate added to support the PRE and PRG modules
2. 24MHz OSC clock option added to the UART, IPG, ECSPI, and
   CAN clock roots.
3. MMDC channel 1 clock gate is now controllable.
4. clock gating added to the LDB_DIx_IPU clocks on i.MX6QP
5. EMI clock root divider fix
6. other updates fo CSCMRx, CSCDRx and CS2CDR registers.

detailed infomation, please refer to the i.MX6QP RM.
Signed-off-by: default avatarBai Ping <ping.bai@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 92e963f5
This diff is collapsed.
......@@ -255,6 +255,20 @@
#define IMX6QDL_CLK_CAAM_ACLK 242
#define IMX6QDL_CLK_CAAM_IPG 243
#define IMX6QDL_CLK_SPDIF_GCLK 244
#define IMX6QDL_CLK_END 245
#define IMX6QDL_CLK_UART_SEL 245
#define IMX6QDL_CLK_IPG_PER_SEL 246
#define IMX6QDL_CLK_ECSPI_SEL 247
#define IMX6QDL_CLK_CAN_SEL 248
#define IMX6QDL_CLK_MMDC_CH1_AXI_CG 249
#define IMX6QDL_CLK_PRE0 250
#define IMX6QDL_CLK_PRE1 251
#define IMX6QDL_CLK_PRE2 252
#define IMX6QDL_CLK_PRE3 253
#define IMX6QDL_CLK_PRG0_AXI 254
#define IMX6QDL_CLK_PRG1_AXI 255
#define IMX6QDL_CLK_PRG0_APB 256
#define IMX6QDL_CLK_PRG1_APB 257
#define IMX6QDL_CLK_PRE_AXI 258
#define IMX6QDL_CLK_END 259
#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
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