Commit ef2a2705 authored by Linus Walleij's avatar Linus Walleij Committed by Arnd Bergmann

ARM: realview: set up cache correctly on the PB11MPCore

The L2 cache comes up in a "safe mode" on the PB11MPCore, as
it has several issues. This sets it up properly with the right
size and associativity, also requiring the outer sync to be
disabled for the machine to boot properly.

Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent f0dba776
...@@ -99,6 +99,19 @@ L2: l2-cache { ...@@ -99,6 +99,19 @@ L2: l2-cache {
<0 31 IRQ_TYPE_LEVEL_HIGH>; <0 31 IRQ_TYPE_LEVEL_HIGH>;
cache-unified; cache-unified;
cache-level = <2>; cache-level = <2>;
/*
* Override default cache size, sets and
* associativity as these may be erroneously set
* up by boot loader(s), probably for safety
* since th outer sync operation can cause the
* cache to hang unless disabled.
*/
cache-size = <1048576>; // 1MB
cache-sets = <4096>;
cache-line-size = <32>;
arm,shared-override;
arm,parity-enable;
arm,outer-sync-disable;
}; };
scu@1f000000 { scu@1f000000 {
......
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