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Commit ef8389a8 authored by Ben Skeggs's avatar Ben Skeggs
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drm/nv50-nvc0: move non-sharable display state into private structure 

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent d82f8e6c
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Inline Side-by-side
Showing with 96 additions and 79 deletions
drivers/gpu/drm/nouveau/nouveau_drv.h
View file @ ef8389a8
......@@ -387,6 +387,7 @@ struct nouveau_pgraph_engine {
};
struct nouveau_display_engine {
void *priv;
int (*early_init)(struct drm_device *);
void (*late_takedown)(struct drm_device *);
int (*create)(struct drm_device *);
......@@ -747,14 +748,6 @@ struct drm_nouveau_private {
struct backlight_device *backlight;
struct nouveau_channel *evo;
u32 evo_alloc;
struct {
struct dcb_entry *dcb;
u16 script;
u32 pclk;
} evo_irq;
struct {
struct dentry *channel_root;
} debugfs;
......
drivers/gpu/drm/nouveau/nv50_crtc.c
View file @ ef8389a8
......@@ -65,7 +65,7 @@ nv50_crtc_blank(struct nouveau_crtc *nv_crtc, bool blanked)
{
struct drm_device *dev = nv_crtc->base.dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_channel *evo = dev_priv->evo;
struct nouveau_channel *evo = nv50_display(dev)->evo;
int index = nv_crtc->index, ret;
NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
......@@ -135,8 +135,7 @@ static int
nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool on, bool update)
{
struct drm_device *dev = nv_crtc->base.dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_channel *evo = dev_priv->evo;
struct nouveau_channel *evo = nv50_display(dev)->evo;
int ret;
NV_DEBUG_KMS(dev, "\n");
......@@ -186,8 +185,7 @@ nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, int scaling_mode, bool update)
struct nouveau_connector *nv_connector =
nouveau_crtc_connector_get(nv_crtc);
struct drm_device *dev = nv_crtc->base.dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_channel *evo = dev_priv->evo;
struct nouveau_channel *evo = nv50_display(dev)->evo;
struct drm_display_mode *native_mode = NULL;
struct drm_display_mode *mode = &nv_crtc->base.mode;
uint32_t outX, outY, horiz, vert;
......@@ -461,8 +459,7 @@ static void
nv50_crtc_commit(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_channel *evo = dev_priv->evo;
struct nouveau_channel *evo = nv50_display(dev)->evo;
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
int ret;
......@@ -496,7 +493,7 @@ nv50_crtc_do_mode_set_base(struct drm_crtc *crtc,
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
struct drm_device *dev = nv_crtc->base.dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_channel *evo = dev_priv->evo;
struct nouveau_channel *evo = nv50_display(dev)->evo;
struct drm_framebuffer *drm_fb = nv_crtc->base.fb;
struct nouveau_framebuffer *fb = nouveau_framebuffer(drm_fb);
int ret, format;
......@@ -619,8 +616,7 @@ nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
struct drm_framebuffer *old_fb)
{
struct drm_device *dev = crtc->dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_channel *evo = dev_priv->evo;
struct nouveau_channel *evo = nv50_display(dev)->evo;
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
struct nouveau_connector *nv_connector = NULL;
uint32_t hsync_dur, vsync_dur, hsync_start_to_end, vsync_start_to_end;
......
drivers/gpu/drm/nouveau/nv50_cursor.c
View file @ ef8389a8
......@@ -36,9 +36,9 @@
static void
nv50_cursor_show(struct nouveau_crtc *nv_crtc, bool update)
{
struct drm_nouveau_private *dev_priv = nv_crtc->base.dev->dev_private;
struct nouveau_channel *evo = dev_priv->evo;
struct drm_device *dev = nv_crtc->base.dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_channel *evo = nv50_display(dev)->evo;
int ret;
NV_DEBUG_KMS(dev, "\n");
......@@ -71,9 +71,9 @@ nv50_cursor_show(struct nouveau_crtc *nv_crtc, bool update)
static void
nv50_cursor_hide(struct nouveau_crtc *nv_crtc, bool update)
{
struct drm_nouveau_private *dev_priv = nv_crtc->base.dev->dev_private;
struct nouveau_channel *evo = dev_priv->evo;
struct drm_device *dev = nv_crtc->base.dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_channel *evo = nv50_display(dev)->evo;
int ret;
NV_DEBUG_KMS(dev, "\n");
......
drivers/gpu/drm/nouveau/nv50_dac.c
View file @ ef8389a8
......@@ -41,8 +41,7 @@ nv50_dac_disconnect(struct drm_encoder *encoder)
{
struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
struct drm_device *dev = encoder->dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_channel *evo = dev_priv->evo;
struct nouveau_channel *evo = nv50_display(dev)->evo;
int ret;
if (!nv_encoder->crtc)
......@@ -216,8 +215,7 @@ nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
{
struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
struct drm_device *dev = encoder->dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_channel *evo = dev_priv->evo;
struct nouveau_channel *evo = nv50_display(dev)->evo;
struct nouveau_crtc *crtc = nouveau_crtc(encoder->crtc);
uint32_t mode_ctl = 0, mode_ctl2 = 0;
int ret;
......
drivers/gpu/drm/nouveau/nv50_display.c
View file @ ef8389a8
......@@ -172,7 +172,7 @@ nv50_display_init(struct drm_device *dev)
ret = nv50_evo_init(dev);
if (ret)
return ret;
evo = dev_priv->evo;
evo = nv50_display(dev)->evo;
nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->vinst >> 8) | 9);
......@@ -201,6 +201,8 @@ nv50_display_init(struct drm_device *dev)
static int nv50_display_disable(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nv50_display *disp = nv50_display(dev);
struct nouveau_channel *evo = disp->evo;
struct drm_crtc *drm_crtc;
int ret, i;
......@@ -212,12 +214,12 @@ static int nv50_display_disable(struct drm_device *dev)
nv50_crtc_blank(crtc, true);
}
ret = RING_SPACE(dev_priv->evo, 2);
ret = RING_SPACE(evo, 2);
if (ret == 0) {
BEGIN_RING(dev_priv->evo, 0, NV50_EVO_UPDATE, 1);
OUT_RING(dev_priv->evo, 0);
BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1);
OUT_RING(evo, 0);
}
FIRE_RING(dev_priv->evo);
FIRE_RING(evo);
/* Almost like ack'ing a vblank interrupt, maybe in the spirit of
* cleaning up?
......@@ -267,10 +269,16 @@ int nv50_display_create(struct drm_device *dev)
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct dcb_table *dcb = &dev_priv->vbios.dcb;
struct drm_connector *connector, *ct;
struct nv50_display *priv;
int ret, i;
NV_DEBUG_KMS(dev, "\n");
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
dev_priv->engine.display.priv = priv;
/* init basic kernel modesetting */
drm_mode_config_init(dev);
......@@ -346,6 +354,7 @@ void
nv50_display_destroy(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nv50_display *disp = nv50_display(dev);
NV_DEBUG_KMS(dev, "\n");
......@@ -354,6 +363,7 @@ nv50_display_destroy(struct drm_device *dev)
nv50_display_disable(dev);
nouveau_irq_unregister(dev, 26);
flush_work_sync(&dev_priv->irq_work);
kfree(disp);
}
static u16
......@@ -469,11 +479,12 @@ static void
nv50_display_unk10_handler(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nv50_display *disp = nv50_display(dev);
u32 unk30 = nv_rd32(dev, 0x610030), mc;
int i, crtc, or, type = OUTPUT_ANY;
NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
dev_priv->evo_irq.dcb = NULL;
disp->irq.dcb = NULL;
nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) & ~8);
......@@ -544,7 +555,7 @@ nv50_display_unk10_handler(struct drm_device *dev)
if (dcb->type == type && (dcb->or & (1 << or))) {
nouveau_bios_run_display_table(dev, dcb, 0, -1);
dev_priv->evo_irq.dcb = dcb;
disp->irq.dcb = dcb;
goto ack;
}
}
......@@ -590,15 +601,16 @@ static void
nv50_display_unk20_handler(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nv50_display *disp = nv50_display(dev);
u32 unk30 = nv_rd32(dev, 0x610030), tmp, pclk, script, mc = 0;
struct dcb_entry *dcb;
int i, crtc, or, type = OUTPUT_ANY;
NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
dcb = dev_priv->evo_irq.dcb;
dcb = disp->irq.dcb;
if (dcb) {
nouveau_bios_run_display_table(dev, dcb, 0, -2);
dev_priv->evo_irq.dcb = NULL;
disp->irq.dcb = NULL;
}
/* CRTC clock change requested? */
......@@ -695,9 +707,9 @@ nv50_display_unk20_handler(struct drm_device *dev)
nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL2(or), 0);
}
dev_priv->evo_irq.dcb = dcb;
dev_priv->evo_irq.pclk = pclk;
dev_priv->evo_irq.script = script;
disp->irq.dcb = dcb;
disp->irq.pclk = pclk;
disp->irq.script = script;
ack:
nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK20);
......@@ -738,13 +750,13 @@ nv50_display_unk40_dp_set_tmds(struct drm_device *dev, struct dcb_entry *dcb)
static void
nv50_display_unk40_handler(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct dcb_entry *dcb = dev_priv->evo_irq.dcb;
u16 script = dev_priv->evo_irq.script;
u32 unk30 = nv_rd32(dev, 0x610030), pclk = dev_priv->evo_irq.pclk;
struct nv50_display *disp = nv50_display(dev);
struct dcb_entry *dcb = disp->irq.dcb;
u16 script = disp->irq.script;
u32 unk30 = nv_rd32(dev, 0x610030), pclk = disp->irq.pclk;
NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
dev_priv->evo_irq.dcb = NULL;
disp->irq.dcb = NULL;
if (!dcb)
goto ack;
......
drivers/gpu/drm/nouveau/nv50_display.h
View file @ ef8389a8
......@@ -35,6 +35,24 @@
#include "nouveau_crtc.h"
#include "nv50_evo.h"
struct nv50_display {
struct nouveau_channel *evo;
u32 evo_alloc;
struct {
struct dcb_entry *dcb;
u16 script;
u32 pclk;
} irq;
};
static inline struct nv50_display *
nv50_display(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
return dev_priv->engine.display.priv;
}
void nv50_display_irq_handler_bh(struct work_struct *work);
int nv50_display_early_init(struct drm_device *dev);
void nv50_display_late_takedown(struct drm_device *dev);
......
drivers/gpu/drm/nouveau/nv50_evo.c
View file @ ef8389a8
......@@ -27,19 +27,20 @@
#include "nouveau_drv.h"
#include "nouveau_dma.h"
#include "nouveau_ramht.h"
#include "nv50_display.h"
static void
nv50_evo_channel_del(struct nouveau_channel **pevo)
{
struct drm_nouveau_private *dev_priv;
struct nouveau_channel *evo = *pevo;
struct nv50_display *disp;
if (!evo)
return;
*pevo = NULL;
dev_priv = evo->dev->dev_private;
dev_priv->evo_alloc &= ~(1 << evo->id);
disp = nv50_display(evo->dev);
disp->evo_alloc &= ~(1 << evo->id);
nouveau_gpuobj_channel_takedown(evo);
nouveau_bo_unmap(evo->pushbuf_bo);
......@@ -57,11 +58,11 @@ nv50_evo_dmaobj_new(struct nouveau_channel *evo, u32 class, u32 name,
u32 flags5)
{
struct drm_nouveau_private *dev_priv = evo->dev->dev_private;
struct drm_device *dev = evo->dev;
struct nv50_display *disp = nv50_display(evo->dev);
struct nouveau_gpuobj *obj = NULL;
int ret;
ret = nouveau_gpuobj_new(dev, dev_priv->evo, 6*4, 32, 0, &obj);
ret = nouveau_gpuobj_new(evo->dev, disp->evo, 6*4, 32, 0, &obj);
if (ret)
return ret;
obj->engine = NVOBJ_ENGINE_DISPLAY;
......@@ -72,7 +73,7 @@ nv50_evo_dmaobj_new(struct nouveau_channel *evo, u32 class, u32 name,
nv_wo32(obj, 12, 0x00000000);
nv_wo32(obj, 16, 0x00000000);
nv_wo32(obj, 20, flags5);
dev_priv->engine.instmem.flush(dev);
dev_priv->engine.instmem.flush(evo->dev);
ret = nouveau_ramht_insert(evo, name, obj);
nouveau_gpuobj_ref(NULL, &obj);
......@@ -86,7 +87,7 @@ nv50_evo_dmaobj_new(struct nouveau_channel *evo, u32 class, u32 name,
static int
nv50_evo_channel_new(struct drm_device *dev, struct nouveau_channel **pevo)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nv50_display *disp = nv50_display(dev);
struct nouveau_channel *evo;
int ret;
......@@ -96,10 +97,10 @@ nv50_evo_channel_new(struct drm_device *dev, struct nouveau_channel **pevo)
*pevo = evo;
for (evo->id = 0; evo->id < 5; evo->id++) {
if (dev_priv->evo_alloc & (1 << evo->id))
if (disp->evo_alloc & (1 << evo->id))
continue;
dev_priv->evo_alloc |= (1 << evo->id);
disp->evo_alloc |= (1 << evo->id);
break;
}
......@@ -138,8 +139,8 @@ nv50_evo_channel_new(struct drm_device *dev, struct nouveau_channel **pevo)
}
/* bind primary evo channel's ramht to the channel */
if (dev_priv->evo && evo != dev_priv->evo)
nouveau_ramht_ref(dev_priv->evo->ramht, &evo->ramht, NULL);
if (disp->evo && evo != disp->evo)
nouveau_ramht_ref(disp->evo->ramht, &evo->ramht, NULL);
return 0;
}
......@@ -216,6 +217,7 @@ static int
nv50_evo_create(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nv50_display *disp = nv50_display(dev);
struct nouveau_gpuobj *ramht = NULL;
struct nouveau_channel *evo;
int ret;
......@@ -223,10 +225,10 @@ nv50_evo_create(struct drm_device *dev)
/* create primary evo channel, the one we use for modesetting
* purporses
*/
ret = nv50_evo_channel_new(dev, &dev_priv->evo);
ret = nv50_evo_channel_new(dev, &disp->evo);
if (ret)
return ret;
evo = dev_priv->evo;
evo = disp->evo;
/* setup object management on it, any other evo channel will
* use this also as there's no per-channel support on the
......@@ -236,28 +238,28 @@ nv50_evo_create(struct drm_device *dev)
NVOBJ_FLAG_ZERO_ALLOC, &evo->ramin);
if (ret) {
NV_ERROR(dev, "Error allocating EVO channel memory: %d\n", ret);
nv50_evo_channel_del(&dev_priv->evo);
nv50_evo_channel_del(&disp->evo);
return ret;
}
ret = drm_mm_init(&evo->ramin_heap, 0, 32768);
if (ret) {
NV_ERROR(dev, "Error initialising EVO PRAMIN heap: %d\n", ret);
nv50_evo_channel_del(&dev_priv->evo);
nv50_evo_channel_del(&disp->evo);
return ret;
}
ret = nouveau_gpuobj_new(dev, evo, 4096, 16, 0, &ramht);
if (ret) {
NV_ERROR(dev, "Unable to allocate EVO RAMHT: %d\n", ret);
nv50_evo_channel_del(&dev_priv->evo);
nv50_evo_channel_del(&disp->evo);
return ret;
}
ret = nouveau_ramht_new(dev, ramht, &evo->ramht);
nouveau_gpuobj_ref(NULL, &ramht);
if (ret) {
nv50_evo_channel_del(&dev_priv->evo);
nv50_evo_channel_del(&disp->evo);
return ret;
}
......@@ -266,28 +268,28 @@ nv50_evo_create(struct drm_device *dev)
ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoFB32, 0xfe, 0x19,
0, 0xffffffff, 0x00000000);
if (ret) {
nv50_evo_channel_del(&dev_priv->evo);
nv50_evo_channel_del(&disp->evo);
return ret;
}
ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoVRAM, 0, 0x19,
0, dev_priv->vram_size, 0x00020000);
if (ret) {
nv50_evo_channel_del(&dev_priv->evo);
nv50_evo_channel_del(&disp->evo);
return ret;
}
ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoVRAM_LP, 0, 0x19,
0, dev_priv->vram_size, 0x00000000);
if (ret) {
nv50_evo_channel_del(&dev_priv->evo);
nv50_evo_channel_del(&disp->evo);
return ret;
}
} else {
ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoFB16, 0x70, 0x19,
0, 0xffffffff, 0x00010000);
if (ret) {
nv50_evo_channel_del(&dev_priv->evo);
nv50_evo_channel_del(&disp->evo);
return ret;
}
......@@ -295,21 +297,21 @@ nv50_evo_create(struct drm_device *dev)
ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoFB32, 0x7a, 0x19,
0, 0xffffffff, 0x00010000);
if (ret) {
nv50_evo_channel_del(&dev_priv->evo);
nv50_evo_channel_del(&disp->evo);
return ret;
}
ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoVRAM, 0, 0x19,
0, dev_priv->vram_size, 0x00010000);
if (ret) {
nv50_evo_channel_del(&dev_priv->evo);
nv50_evo_channel_del(&disp->evo);
return ret;
}
ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoVRAM_LP, 0, 0x19,
0, dev_priv->vram_size, 0x00010000);
if (ret) {
nv50_evo_channel_del(&dev_priv->evo);
nv50_evo_channel_del(&disp->evo);
return ret;
}
}
......@@ -320,25 +322,25 @@ nv50_evo_create(struct drm_device *dev)
int
nv50_evo_init(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nv50_display *disp = nv50_display(dev);
int ret;
if (!dev_priv->evo) {
if (!disp->evo) {
ret = nv50_evo_create(dev);
if (ret)
return ret;
}
return nv50_evo_channel_init(dev_priv->evo);
return nv50_evo_channel_init(disp->evo);
}
void
nv50_evo_fini(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nv50_display *disp = nv50_display(dev);
if (dev_priv->evo) {
nv50_evo_channel_fini(dev_priv->evo);
nv50_evo_channel_del(&dev_priv->evo);
if (disp->evo) {
nv50_evo_channel_fini(disp->evo);
nv50_evo_channel_del(&disp->evo);
}
}
drivers/gpu/drm/nouveau/nv50_evo.h
View file @ ef8389a8
......@@ -31,7 +31,7 @@ int nv50_evo_init(struct drm_device *dev);
void nv50_evo_fini(struct drm_device *dev);
int nv50_evo_dmaobj_new(struct nouveau_channel *, u32 class, u32 name,
u32 tile_flags, u32 magic_flags,
u32 offset, u32 limit);
u32 offset, u32 limit, u32 flags5);
#define NV50_EVO_UPDATE 0x00000080
#define NV50_EVO_UNK84 0x00000084
......
drivers/gpu/drm/nouveau/nv50_sor.c
View file @ ef8389a8
......@@ -41,8 +41,7 @@ nv50_sor_disconnect(struct drm_encoder *encoder)
{
struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
struct drm_device *dev = encoder->dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_channel *evo = dev_priv->evo;
struct nouveau_channel *evo = nv50_display(dev)->evo;
int ret;
if (!nv_encoder->crtc)
......@@ -184,8 +183,7 @@ static void
nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{
struct drm_nouveau_private *dev_priv = encoder->dev->dev_private;
struct nouveau_channel *evo = dev_priv->evo;
struct nouveau_channel *evo = nv50_display(encoder->dev)->evo;
struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
struct drm_device *dev = encoder->dev;
struct nouveau_crtc *crtc = nouveau_crtc(encoder->crtc);
......
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