Commit eff1a59c authored by Michael Wu's avatar Michael Wu Committed by David S. Miller

[P54]: add mac80211-based driver for prism54 softmac hardware

Signed-off-by: default avatarMichael Wu <flamingice@sourmilk.net>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 0795af57
......@@ -3060,6 +3060,14 @@ L: kpreempt-tech@lists.sourceforge.net
W: ftp://ftp.kernel.org/pub/linux/kernel/people/rml/preempt-kernel
S: Supported
P54 WIRELESS DRIVER
P: Michael Wu
M: flamingice@sourmilk.net
L: linux-wireless@vger.kernel.org
W: http://prism54.org
T: git kernel.org:/pub/scm/linux/kernel/git/mwu/mac80211-drivers.git
S: Maintained
PRISM54 WIRELESS DRIVER
P: Luis R. Rodriguez
M: mcgrof@gmail.com
......
......@@ -577,6 +577,19 @@ config ADM8211
Thanks to Infineon-ADMtek for their support of this driver.
config P54_COMMON
tristate "Softmac Prism54 support"
depends on MAC80211 && WLAN_80211 && FW_LOADER && EXPERIMENTAL
config P54_USB
tristate "Prism54 USB support"
depends on P54_COMMON && USB
select CRC32
config P54_PCI
tristate "Prism54 PCI support"
depends on P54_COMMON && PCI
source "drivers/net/wireless/iwlwifi/Kconfig"
source "drivers/net/wireless/hostap/Kconfig"
source "drivers/net/wireless/bcm43xx/Kconfig"
......
......@@ -54,3 +54,7 @@ obj-$(CONFIG_ADM8211) += adm8211.o
obj-$(CONFIG_IWLWIFI) += iwlwifi/
obj-$(CONFIG_RT2X00) += rt2x00/
obj-$(CONFIG_P54_COMMON) += p54common.o
obj-$(CONFIG_P54_USB) += p54usb.o
obj-$(CONFIG_P54_PCI) += p54pci.o
This diff is collapsed.
#ifndef PRISM54_H
#define PRISM54_H
/*
* Shared defines for all mac80211 Prism54 code
*
* Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
*
* Based on the islsm (softmac prism54) driver, which is:
* Copyright 2004-2006 Jean-Baptiste Note <jbnote@gmail.com>, et al.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
enum control_frame_types {
P54_CONTROL_TYPE_FILTER_SET = 0,
P54_CONTROL_TYPE_CHANNEL_CHANGE,
P54_CONTROL_TYPE_FREQDONE,
P54_CONTROL_TYPE_DCFINIT,
P54_CONTROL_TYPE_FREEQUEUE = 7,
P54_CONTROL_TYPE_TXDONE,
P54_CONTROL_TYPE_PING,
P54_CONTROL_TYPE_STAT_READBACK,
P54_CONTROL_TYPE_BBP,
P54_CONTROL_TYPE_EEPROM_READBACK,
P54_CONTROL_TYPE_LED
};
struct p54_control_hdr {
__le16 magic1;
__le16 len;
__le32 req_id;
__le16 type; /* enum control_frame_types */
u8 retry1;
u8 retry2;
u8 data[0];
} __attribute__ ((packed));
#define EEPROM_READBACK_LEN (sizeof(struct p54_control_hdr) + 4 /* p54_eeprom_lm86 */)
#define MAX_RX_SIZE (IEEE80211_MAX_RTS_THRESHOLD + sizeof(struct p54_control_hdr) + 20 /* length of struct p54_rx_hdr */ + 16 )
#define ISL38XX_DEV_FIRMWARE_ADDR 0x20000
struct p54_common {
u32 rx_start;
u32 rx_end;
struct sk_buff_head tx_queue;
void (*tx)(struct ieee80211_hw *dev, struct p54_control_hdr *data,
size_t len, int free_on_tx);
int (*open)(struct ieee80211_hw *dev);
void (*stop)(struct ieee80211_hw *dev);
int mode;
u8 *mac_addr;
struct pda_iq_autocal_entry *iq_autocal;
unsigned int iq_autocal_len;
struct pda_channel_output_limit *output_limit;
unsigned int output_limit_len;
struct pda_pa_curve_data *curve_data;
__le16 rxhw;
u8 version;
unsigned int tx_hdr_len;
void *cached_vdcf;
unsigned int fw_var;
/* FIXME: this channels/modes/rates stuff sucks */
struct ieee80211_channel channels[14];
struct ieee80211_rate rates[12];
struct ieee80211_hw_mode modes[2];
struct ieee80211_tx_queue_stats tx_stats;
};
int p54_rx(struct ieee80211_hw *dev, struct sk_buff *skb);
void p54_parse_firmware(struct ieee80211_hw *dev, const struct firmware *fw);
int p54_parse_eeprom(struct ieee80211_hw *dev, void *eeprom, int len);
void p54_fill_eeprom_readback(struct p54_control_hdr *hdr);
struct ieee80211_hw *p54_init_common(size_t priv_data_len);
void p54_free_common(struct ieee80211_hw *dev);
#endif /* PRISM54_H */
This diff is collapsed.
#ifndef PRISM54COMMON_H
#define PRISM54COMMON_H
/*
* Common code specific definitions for mac80211 Prism54 drivers
*
* Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
* Copyright (c) 2007, Christian Lamparter <chunkeey@web.de>
*
* Based on the islsm (softmac prism54) driver, which is:
* Copyright 2004-2006 Jean-Baptiste Note <jbnote@gmail.com>, et al.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
struct bootrec {
__le32 code;
__le32 len;
u32 data[0];
} __attribute__((packed));
struct bootrec_exp_if {
__le16 role;
__le16 if_id;
__le16 variant;
__le16 btm_compat;
__le16 top_compat;
} __attribute__((packed));
#define BR_CODE_MIN 0x80000000
#define BR_CODE_COMPONENT_ID 0x80000001
#define BR_CODE_COMPONENT_VERSION 0x80000002
#define BR_CODE_DEPENDENT_IF 0x80000003
#define BR_CODE_EXPOSED_IF 0x80000004
#define BR_CODE_DESCR 0x80000101
#define BR_CODE_MAX 0x8FFFFFFF
#define BR_CODE_END_OF_BRA 0xFF0000FF
#define LEGACY_BR_CODE_END_OF_BRA 0xFFFFFFFF
#define FW_FMAC 0x464d4143
#define FW_LM86 0x4c4d3836
#define FW_LM87 0x4c4d3837
#define FW_LM20 0x4c4d3230
/* PDA defines are Copyright (C) 2005 Nokia Corporation (taken from islsm_pda.h) */
struct pda_entry {
__le16 len; /* includes both code and data */
__le16 code;
u8 data[0];
} __attribute__ ((packed));
struct eeprom_pda_wrap {
u32 magic;
u16 pad;
u16 len;
u32 arm_opcode;
u8 data[0];
} __attribute__ ((packed));
struct pda_iq_autocal_entry {
__le16 freq;
__le16 iq_param[4];
} __attribute__ ((packed));
struct pda_channel_output_limit {
__le16 freq;
u8 val_bpsk;
u8 val_qpsk;
u8 val_16qam;
u8 val_64qam;
u8 rate_set_mask;
u8 rate_set_size;
} __attribute__ ((packed));
struct pda_pa_curve_data_sample_rev0 {
u8 rf_power;
u8 pa_detector;
u8 pcv;
} __attribute__ ((packed));
struct pda_pa_curve_data_sample_rev1 {
u8 rf_power;
u8 pa_detector;
u8 data_barker;
u8 data_bpsk;
u8 data_qpsk;
u8 data_16qam;
u8 data_64qam;
u8 padding;
} __attribute__ ((packed));
struct pda_pa_curve_data {
u8 cal_method_rev;
u8 channels;
u8 points_per_channel;
u8 padding;
u8 data[0];
} __attribute__ ((packed));
/*
* this defines the PDR codes used to build PDAs as defined in document
* number 553155. The current implementation mirrors version 1.1 of the
* document and lists only PDRs supported by the ARM platform.
*/
/* common and choice range (0x0000 - 0x0fff) */
#define PDR_END 0x0000
#define PDR_MANUFACTURING_PART_NUMBER 0x0001
#define PDR_PDA_VERSION 0x0002
#define PDR_NIC_SERIAL_NUMBER 0x0003
#define PDR_MAC_ADDRESS 0x0101
#define PDR_REGULATORY_DOMAIN_LIST 0x0103
#define PDR_TEMPERATURE_TYPE 0x0107
#define PDR_PRISM_PCI_IDENTIFIER 0x0402
/* ARM range (0x1000 - 0x1fff) */
#define PDR_COUNTRY_INFORMATION 0x1000
#define PDR_INTERFACE_LIST 0x1001
#define PDR_HARDWARE_PLATFORM_COMPONENT_ID 0x1002
#define PDR_OEM_NAME 0x1003
#define PDR_PRODUCT_NAME 0x1004
#define PDR_UTF8_OEM_NAME 0x1005
#define PDR_UTF8_PRODUCT_NAME 0x1006
#define PDR_COUNTRY_LIST 0x1007
#define PDR_DEFAULT_COUNTRY 0x1008
#define PDR_ANTENNA_GAIN 0x1100
#define PDR_PRISM_INDIGO_PA_CALIBRATION_DATA 0x1901
#define PDR_RSSI_LINEAR_APPROXIMATION 0x1902
#define PDR_PRISM_PA_CAL_OUTPUT_POWER_LIMITS 0x1903
#define PDR_PRISM_PA_CAL_CURVE_DATA 0x1904
#define PDR_RSSI_LINEAR_APPROXIMATION_DUAL_BAND 0x1905
#define PDR_PRISM_ZIF_TX_IQ_CALIBRATION 0x1906
#define PDR_REGULATORY_POWER_LIMITS 0x1907
#define PDR_RSSI_LINEAR_APPROXIMATION_EXTENDED 0x1908
#define PDR_RADIATED_TRANSMISSION_CORRECTION 0x1909
#define PDR_PRISM_TX_IQ_CALIBRATION 0x190a
/* reserved range (0x2000 - 0x7fff) */
/* customer range (0x8000 - 0xffff) */
#define PDR_BASEBAND_REGISTERS 0x8000
#define PDR_PER_CHANNEL_BASEBAND_REGISTERS 0x8001
/* stored in skb->cb */
struct memrecord {
u32 start_addr;
u32 end_addr;
struct ieee80211_tx_control *control;
};
struct p54_eeprom_lm86 {
__le16 offset;
__le16 len;
u8 data[0];
} __attribute__ ((packed));
struct p54_rx_hdr {
__le16 magic;
__le16 len;
__le16 freq;
u8 antenna;
u8 rate;
u8 rssi;
u8 quality;
u16 unknown2;
__le64 timestamp;
u8 data[0];
} __attribute__ ((packed));
struct p54_frame_sent_hdr {
u8 status;
u8 retries;
__le16 ack_rssi;
__le16 seq;
u16 rate;
} __attribute__ ((packed));
struct p54_tx_control_allocdata {
u8 rateset[8];
u16 padding;
u8 wep_key_present;
u8 wep_key_len;
u8 wep_key[16];
__le32 frame_type;
u32 padding2;
__le16 magic4;
u8 antenna;
u8 output_power;
__le32 magic5;
u8 align[0];
} __attribute__ ((packed));
struct p54_tx_control_filter {
__le16 filter_type;
u8 dst[ETH_ALEN];
u8 src[ETH_ALEN];
u8 antenna;
u8 debug;
__le32 magic3;
u8 rates[8]; // FIXME: what's this for?
__le32 rx_addr;
__le16 max_rx;
__le16 rxhw;
__le16 magic8;
__le16 magic9;
} __attribute__ ((packed));
struct p54_tx_control_channel {
__le16 magic1;
__le16 magic2;
u8 padding1[20];
struct pda_iq_autocal_entry iq_autocal;
u8 pa_points_per_curve;
u8 val_barker;
u8 val_bpsk;
u8 val_qpsk;
u8 val_16qam;
u8 val_64qam;
struct pda_pa_curve_data_sample_rev1 curve_data[0];
/* additional padding/data after curve_data */
} __attribute__ ((packed));
struct p54_tx_control_led {
__le16 mode;
__le16 led_temporary;
__le16 led_permanent;
__le16 duration;
} __attribute__ ((packed));
struct p54_tx_vdcf_queues {
__le16 aifs;
__le16 cwmin;
__le16 cwmax;
__le16 txop;
} __attribute__ ((packed));
struct p54_tx_control_vdcf {
u8 padding;
u8 slottime;
u8 magic1;
u8 magic2;
struct p54_tx_vdcf_queues queue[8];
u8 pad2[4];
__le16 frameburst;
} __attribute__ ((packed));
static const struct ieee80211_rate p54_rates[] = {
{ .rate = 10,
.val = 0,
.val2 = 0x10,
.flags = IEEE80211_RATE_CCK_2 },
{ .rate = 20,
.val = 1,
.val2 = 0x11,
.flags = IEEE80211_RATE_CCK_2 },
{ .rate = 55,
.val = 2,
.val2 = 0x12,
.flags = IEEE80211_RATE_CCK_2 },
{ .rate = 110,
.val = 3,
.val2 = 0x13,
.flags = IEEE80211_RATE_CCK_2 },
{ .rate = 60,
.val = 4,
.flags = IEEE80211_RATE_OFDM },
{ .rate = 90,
.val = 5,
.flags = IEEE80211_RATE_OFDM },
{ .rate = 120,
.val = 6,
.flags = IEEE80211_RATE_OFDM },
{ .rate = 180,
.val = 7,
.flags = IEEE80211_RATE_OFDM },
{ .rate = 240,
.val = 8,
.flags = IEEE80211_RATE_OFDM },
{ .rate = 360,
.val = 9,
.flags = IEEE80211_RATE_OFDM },
{ .rate = 480,
.val = 10,
.flags = IEEE80211_RATE_OFDM },
{ .rate = 540,
.val = 11,
.flags = IEEE80211_RATE_OFDM },
};
// TODO: just generate this..
static const struct ieee80211_channel p54_channels[] = {
{ .chan = 1,
.freq = 2412},
{ .chan = 2,
.freq = 2417},
{ .chan = 3,
.freq = 2422},
{ .chan = 4,
.freq = 2427},
{ .chan = 5,
.freq = 2432},
{ .chan = 6,
.freq = 2437},
{ .chan = 7,
.freq = 2442},
{ .chan = 8,
.freq = 2447},
{ .chan = 9,
.freq = 2452},
{ .chan = 10,
.freq = 2457},
{ .chan = 11,
.freq = 2462},
{ .chan = 12,
.freq = 2467},
{ .chan = 13,
.freq = 2472},
{ .chan = 14,
.freq = 2484}
};
#endif /* PRISM54COMMON_H */
This diff is collapsed.
#ifndef PRISM54PCI_H
#define PRISM54PCI_H
/*
* Defines for PCI based mac80211 Prism54 driver
*
* Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
*
* Based on the islsm (softmac prism54) driver, which is:
* Copyright 2004-2006 Jean-Baptiste Note <jbnote@gmail.com>, et al.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* Device Interrupt register bits */
#define ISL38XX_DEV_INT_RESET 0x0001
#define ISL38XX_DEV_INT_UPDATE 0x0002
#define ISL38XX_DEV_INT_WAKEUP 0x0008
#define ISL38XX_DEV_INT_SLEEP 0x0010
#define ISL38XX_DEV_INT_ABORT 0x0020
/* these two only used in USB */
#define ISL38XX_DEV_INT_DATA 0x0040
#define ISL38XX_DEV_INT_MGMT 0x0080
#define ISL38XX_DEV_INT_PCIUART_CTS 0x4000
#define ISL38XX_DEV_INT_PCIUART_DR 0x8000
/* Interrupt Identification/Acknowledge/Enable register bits */
#define ISL38XX_INT_IDENT_UPDATE 0x0002
#define ISL38XX_INT_IDENT_INIT 0x0004
#define ISL38XX_INT_IDENT_WAKEUP 0x0008
#define ISL38XX_INT_IDENT_SLEEP 0x0010
#define ISL38XX_INT_IDENT_PCIUART_CTS 0x4000
#define ISL38XX_INT_IDENT_PCIUART_DR 0x8000
/* Control/Status register bits */
#define ISL38XX_CTRL_STAT_SLEEPMODE 0x00000200
#define ISL38XX_CTRL_STAT_CLKRUN 0x00800000
#define ISL38XX_CTRL_STAT_RESET 0x10000000
#define ISL38XX_CTRL_STAT_RAMBOOT 0x20000000
#define ISL38XX_CTRL_STAT_STARTHALTED 0x40000000
#define ISL38XX_CTRL_STAT_HOST_OVERRIDE 0x80000000
struct p54p_csr {
__le32 dev_int;
u8 unused_1[12];
__le32 int_ident;
__le32 int_ack;
__le32 int_enable;
u8 unused_2[4];
union {
__le32 ring_control_base;
__le32 gen_purp_com[2];
};
u8 unused_3[8];
__le32 direct_mem_base;
u8 unused_4[44];
__le32 dma_addr;
__le32 dma_len;
__le32 dma_ctrl;
u8 unused_5[12];
__le32 ctrl_stat;
u8 unused_6[1924];
u8 cardbus_cis[0x800];
u8 direct_mem_win[0x1000];
} __attribute__ ((packed));
/* usb backend only needs the register defines above */
#ifndef PRISM54USB_H
struct p54p_desc {
__le32 host_addr;
__le32 device_addr;
__le16 len;
__le16 flags;
} __attribute__ ((packed));
struct p54p_ring_control {
__le32 host_idx[4];
__le32 device_idx[4];
struct p54p_desc rx_data[8];
struct p54p_desc tx_data[32];
struct p54p_desc rx_mgmt[4];
struct p54p_desc tx_mgmt[4];
} __attribute__ ((packed));
#define P54P_READ(r) __raw_readl(&priv->map->r)
#define P54P_WRITE(r, val) __raw_writel((__force u32)(val), &priv->map->r)
struct p54p_priv {
struct p54_common common;
struct pci_dev *pdev;
struct p54p_csr __iomem *map;
spinlock_t lock;
struct p54p_ring_control *ring_control;
dma_addr_t ring_control_dma;
u32 rx_idx, tx_idx;
struct sk_buff *rx_buf[8];
void *tx_buf[32];
struct completion boot_comp;
};
#endif /* PRISM54USB_H */
#endif /* PRISM54PCI_H */
This diff is collapsed.
#ifndef PRISM54USB_H
#define PRISM54USB_H
/*
* Defines for USB based mac80211 Prism54 driver
*
* Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
*
* Based on the islsm (softmac prism54) driver, which is:
* Copyright 2004-2006 Jean-Baptiste Note <jbnote@gmail.com>, et al.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* for isl3886 register definitions used on ver 1 devices */
#include "p54pci.h"
#include "net2280.h"
/* pci */
#define NET2280_BASE 0x10000000
#define NET2280_BASE2 0x20000000
/* gpio */
#define P54U_BRG_POWER_UP (1 << GPIO0_DATA)
#define P54U_BRG_POWER_DOWN (1 << GPIO1_DATA)
/* devinit */
#define NET2280_CLK_4Mhz (15 << LOCAL_CLOCK_FREQUENCY)
#define NET2280_CLK_30Mhz (2 << LOCAL_CLOCK_FREQUENCY)
#define NET2280_CLK_60Mhz (1 << LOCAL_CLOCK_FREQUENCY)
#define NET2280_CLK_STOP (0 << LOCAL_CLOCK_FREQUENCY)
#define NET2280_PCI_ENABLE (1 << PCI_ENABLE)
#define NET2280_PCI_SOFT_RESET (1 << PCI_SOFT_RESET)
/* endpoints */
#define NET2280_CLEAR_NAK_OUT_PACKETS_MODE (1 << CLEAR_NAK_OUT_PACKETS_MODE)
#define NET2280_FIFO_FLUSH (1 << FIFO_FLUSH)
/* irq */
#define NET2280_USB_INTERRUPT_ENABLE (1 << USB_INTERRUPT_ENABLE)
#define NET2280_PCI_INTA_INTERRUPT (1 << PCI_INTA_INTERRUPT)
#define NET2280_PCI_INTA_INTERRUPT_ENABLE (1 << PCI_INTA_INTERRUPT_ENABLE)
/* registers */
#define NET2280_DEVINIT 0x00
#define NET2280_USBIRQENB1 0x24
#define NET2280_IRQSTAT1 0x2c
#define NET2280_FIFOCTL 0x38
#define NET2280_GPIOCTL 0x50
#define NET2280_RELNUM 0x88
#define NET2280_EPA_RSP 0x324
#define NET2280_EPA_STAT 0x32c
#define NET2280_EPB_STAT 0x34c
#define NET2280_EPC_RSP 0x364
#define NET2280_EPC_STAT 0x36c
#define NET2280_EPD_STAT 0x38c
#define NET2280_EPA_CFG 0x320
#define NET2280_EPB_CFG 0x340
#define NET2280_EPC_CFG 0x360
#define NET2280_EPD_CFG 0x380
#define NET2280_EPE_CFG 0x3A0
#define NET2280_EPF_CFG 0x3C0
#define P54U_DEV_BASE 0x40000000
struct net2280_tx_hdr {
__le32 device_addr;
__le16 len;
__le16 follower; /* ? */
u8 padding[8];
} __attribute__((packed));
/* Some flags for the isl hardware registers controlling DMA inside the
* chip */
#define ISL38XX_DMA_STATUS_DONE 0x00000001
#define ISL38XX_DMA_STATUS_READY 0x00000002
#define NET2280_EPA_FIFO_PCI_ADDR 0x20000000
#define ISL38XX_DMA_MASTER_CONTROL_TRIGGER 0x00000004
enum net2280_op_type {
NET2280_BRG_U32 = 0x001F,
NET2280_BRG_CFG_U32 = 0x000F,
NET2280_BRG_CFG_U16 = 0x0003,
NET2280_DEV_U32 = 0x080F,
NET2280_DEV_CFG_U32 = 0x088F,
NET2280_DEV_CFG_U16 = 0x0883
};
#define P54U_FW_BLOCK 2048
#define X2_SIGNATURE "x2 "
#define X2_SIGNATURE_SIZE 4
struct x2_header {
u8 signature[X2_SIGNATURE_SIZE];
__le32 fw_load_addr;
__le32 fw_length;
__le32 crc;
} __attribute__((packed));
/* pipes 3 and 4 are not used by the driver */
#define P54U_PIPE_NUMBER 9
enum p54u_pipe_addr {
P54U_PIPE_DATA = 0x01,
P54U_PIPE_MGMT = 0x02,
P54U_PIPE_3 = 0x03,
P54U_PIPE_4 = 0x04,
P54U_PIPE_BRG = 0x0d,
P54U_PIPE_DEV = 0x0e,
P54U_PIPE_INT = 0x0f
};
struct p54u_rx_info {
struct urb *urb;
struct ieee80211_hw *dev;
};
struct p54u_priv {
struct p54_common common;
struct usb_device *udev;
enum {
P54U_NET2280 = 0,
P54U_3887
} hw_type;
spinlock_t lock;
struct sk_buff_head rx_queue;
};
#endif /* PRISM54USB_H */
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