Commit f0f2338a authored by Daniel Mack's avatar Daniel Mack Committed by Mark Brown

ASoC: cs4270: Set auto-increment bit for register writes

The CS4270 does not by default increment the register address on
consecutive writes. During normal operation it doesn't matter as all
register accesses are done individually. At resume time after suspend,
however, the regcache code gathers the biggest possible block of
registers to sync and sends them one on one go.

To fix this, set the INCR bit in all cases.
Signed-off-by: default avatarDaniel Mack <daniel@zonque.org>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent c47255b6
......@@ -642,6 +642,7 @@ static const struct regmap_config cs4270_regmap = {
.reg_defaults = cs4270_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(cs4270_reg_defaults),
.cache_type = REGCACHE_RBTREE,
.write_flag_mask = CS4270_I2C_INCR,
.readable_reg = cs4270_reg_is_readable,
.volatile_reg = cs4270_reg_is_volatile,
......
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