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Commit f2e442fd authored by Manuel Lauss's avatar Manuel Lauss Committed by Ralf Baechle
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MIPS: Alchemy: clean DMA code of CONFIG_SOC_AU1??? defines 

This patch gets rid of all CONFIG_SOC_AU1XXX defines in
DMA/DBDMA-related code.
Signed-off-by: default avatarManuel Lauss <manuel.lauss@googlemail.com>
To: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/2704/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent d4f07ae7
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Showing with 207 additions and 236 deletions
arch/mips/alchemy/common/dbdma.c
View file @ f2e442fd
This diff is collapsed.
arch/mips/alchemy/common/dma.c
View file @ f2e442fd
......@@ -40,8 +40,6 @@
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1000_dma.h>
#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \
defined(CONFIG_SOC_AU1100)
/*
* A note on resource allocation:
*
......@@ -170,13 +168,13 @@ int request_au1000_dma(int dev_id, const char *dev_str,
const struct dma_dev *dev;
int i, ret;
#if defined(CONFIG_SOC_AU1100)
if (dev_id < 0 || dev_id >= (DMA_NUM_DEV + DMA_NUM_DEV_BANK2))
return -EINVAL;
#else
if (dev_id < 0 || dev_id >= DMA_NUM_DEV)
return -EINVAL;
#endif
if (alchemy_get_cputype() == ALCHEMY_CPU_AU1100) {
if (dev_id < 0 || dev_id >= (DMA_NUM_DEV + DMA_NUM_DEV_BANK2))
return -EINVAL;
} else {
if (dev_id < 0 || dev_id >= DMA_NUM_DEV)
return -EINVAL;
}
for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++)
if (au1000_dma_table[i].dev_id < 0)
......@@ -239,30 +237,28 @@ EXPORT_SYMBOL(free_au1000_dma);
static int __init au1000_dma_init(void)
{
int base, i;
switch (alchemy_get_cputype()) {
case ALCHEMY_CPU_AU1000:
base = AU1000_DMA_INT_BASE;
break;
case ALCHEMY_CPU_AU1500:
base = AU1500_DMA_INT_BASE;
break;
case ALCHEMY_CPU_AU1100:
base = AU1100_DMA_INT_BASE;
break;
default:
goto out;
}
for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++)
au1000_dma_table[i].irq = base + i;
printk(KERN_INFO "Alchemy DMA initialized\n");
int base, i;
switch (alchemy_get_cputype()) {
case ALCHEMY_CPU_AU1000:
base = AU1000_DMA_INT_BASE;
break;
case ALCHEMY_CPU_AU1500:
base = AU1500_DMA_INT_BASE;
break;
case ALCHEMY_CPU_AU1100:
base = AU1100_DMA_INT_BASE;
break;
default:
goto out;
}
for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++)
au1000_dma_table[i].irq = base + i;
printk(KERN_INFO "Alchemy DMA initialized\n");
out:
return 0;
return 0;
}
arch_initcall(au1000_dma_init);
#endif /* AU1000 AU1500 AU1100 */
arch/mips/alchemy/common/platform.c
View file @ f2e442fd
......@@ -263,13 +263,13 @@ static struct resource au1200_mmc0_resources[] = {
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = DSCR_CMD0_SDMS_TX0,
.end = DSCR_CMD0_SDMS_TX0,
.start = AU1200_DSCR_CMD0_SDMS_TX0,
.end = AU1200_DSCR_CMD0_SDMS_TX0,
.flags = IORESOURCE_DMA,
},
[3] = {
.start = DSCR_CMD0_SDMS_RX0,
.end = DSCR_CMD0_SDMS_RX0,
.start = AU1200_DSCR_CMD0_SDMS_RX0,
.end = AU1200_DSCR_CMD0_SDMS_RX0,
.flags = IORESOURCE_DMA,
}
};
......@@ -299,13 +299,13 @@ static struct resource au1200_mmc1_resources[] = {
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = DSCR_CMD0_SDMS_TX1,
.end = DSCR_CMD0_SDMS_TX1,
.start = AU1200_DSCR_CMD0_SDMS_TX1,
.end = AU1200_DSCR_CMD0_SDMS_TX1,
.flags = IORESOURCE_DMA,
},
[3] = {
.start = DSCR_CMD0_SDMS_RX1,
.end = DSCR_CMD0_SDMS_RX1,
.start = AU1200_DSCR_CMD0_SDMS_RX1,
.end = AU1200_DSCR_CMD0_SDMS_RX1,
.flags = IORESOURCE_DMA,
}
};
......
arch/mips/alchemy/devboards/db1200/platform.c
View file @ f2e442fd
......@@ -215,8 +215,8 @@ static struct resource db1200_ide_res[] = {
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = DSCR_CMD0_DMA_REQ1,
.end = DSCR_CMD0_DMA_REQ1,
.start = AU1200_DSCR_CMD0_DMA_REQ1,
.end = AU1200_DSCR_CMD0_DMA_REQ1,
.flags = IORESOURCE_DMA,
},
};
......@@ -358,13 +358,13 @@ static struct resource au1200_psc0_res[] = {
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = DSCR_CMD0_PSC0_TX,
.end = DSCR_CMD0_PSC0_TX,
.start = AU1200_DSCR_CMD0_PSC0_TX,
.end = AU1200_DSCR_CMD0_PSC0_TX,
.flags = IORESOURCE_DMA,
},
[3] = {
.start = DSCR_CMD0_PSC0_RX,
.end = DSCR_CMD0_PSC0_RX,
.start = AU1200_DSCR_CMD0_PSC0_RX,
.end = AU1200_DSCR_CMD0_PSC0_RX,
.flags = IORESOURCE_DMA,
},
};
......@@ -416,13 +416,13 @@ static struct resource au1200_psc1_res[] = {
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = DSCR_CMD0_PSC1_TX,
.end = DSCR_CMD0_PSC1_TX,
.start = AU1200_DSCR_CMD0_PSC1_TX,
.end = AU1200_DSCR_CMD0_PSC1_TX,
.flags = IORESOURCE_DMA,
},
[3] = {
.start = DSCR_CMD0_PSC1_RX,
.end = DSCR_CMD0_PSC1_RX,
.start = AU1200_DSCR_CMD0_PSC1_RX,
.end = AU1200_DSCR_CMD0_PSC1_RX,
.flags = IORESOURCE_DMA,
},
};
......
arch/mips/alchemy/devboards/pb1200/platform.c
View file @ f2e442fd
......@@ -118,8 +118,8 @@ static struct resource ide_resources[] = {
.flags = IORESOURCE_IRQ
},
[2] = {
.start = DSCR_CMD0_DMA_REQ1,
.end = DSCR_CMD0_DMA_REQ1,
.start = AU1200_DSCR_CMD0_DMA_REQ1,
.end = AU1200_DSCR_CMD0_DMA_REQ1,
.flags = IORESOURCE_DMA,
},
};
......
arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
View file @ f2e442fd
......@@ -126,66 +126,62 @@ typedef volatile struct au1xxx_ddma_desc {
#define SW_STATUS_INUSE (1 << 0)
/* Command 0 device IDs. */
#ifdef CONFIG_SOC_AU1550
#define DSCR_CMD0_UART0_TX 0
#define DSCR_CMD0_UART0_RX 1
#define DSCR_CMD0_UART3_TX 2
#define DSCR_CMD0_UART3_RX 3
#define DSCR_CMD0_DMA_REQ0 4
#define DSCR_CMD0_DMA_REQ1 5
#define DSCR_CMD0_DMA_REQ2 6
#define DSCR_CMD0_DMA_REQ3 7
#define DSCR_CMD0_USBDEV_RX0 8
#define DSCR_CMD0_USBDEV_TX0 9
#define DSCR_CMD0_USBDEV_TX1 10
#define DSCR_CMD0_USBDEV_TX2 11
#define DSCR_CMD0_USBDEV_RX3 12
#define DSCR_CMD0_USBDEV_RX4 13
#define DSCR_CMD0_PSC0_TX 14
#define DSCR_CMD0_PSC0_RX 15
#define DSCR_CMD0_PSC1_TX 16
#define DSCR_CMD0_PSC1_RX 17
#define DSCR_CMD0_PSC2_TX 18
#define DSCR_CMD0_PSC2_RX 19
#define DSCR_CMD0_PSC3_TX 20
#define DSCR_CMD0_PSC3_RX 21
#define DSCR_CMD0_PCI_WRITE 22
#define DSCR_CMD0_NAND_FLASH 23
#define DSCR_CMD0_MAC0_RX 24
#define DSCR_CMD0_MAC0_TX 25
#define DSCR_CMD0_MAC1_RX 26
#define DSCR_CMD0_MAC1_TX 27
#endif /* CONFIG_SOC_AU1550 */
#ifdef CONFIG_SOC_AU1200
#define DSCR_CMD0_UART0_TX 0
#define DSCR_CMD0_UART0_RX 1
#define DSCR_CMD0_UART1_TX 2
#define DSCR_CMD0_UART1_RX 3
#define DSCR_CMD0_DMA_REQ0 4
#define DSCR_CMD0_DMA_REQ1 5
#define DSCR_CMD0_MAE_BE 6
#define DSCR_CMD0_MAE_FE 7
#define DSCR_CMD0_SDMS_TX0 8
#define DSCR_CMD0_SDMS_RX0 9
#define DSCR_CMD0_SDMS_TX1 10
#define DSCR_CMD0_SDMS_RX1 11
#define DSCR_CMD0_AES_TX 13
#define DSCR_CMD0_AES_RX 12
#define DSCR_CMD0_PSC0_TX 14
#define DSCR_CMD0_PSC0_RX 15
#define DSCR_CMD0_PSC1_TX 16
#define DSCR_CMD0_PSC1_RX 17
#define DSCR_CMD0_CIM_RXA 18
#define DSCR_CMD0_CIM_RXB 19
#define DSCR_CMD0_CIM_RXC 20
#define DSCR_CMD0_MAE_BOTH 21
#define DSCR_CMD0_LCD 22
#define DSCR_CMD0_NAND_FLASH 23
#define DSCR_CMD0_PSC0_SYNC 24
#define DSCR_CMD0_PSC1_SYNC 25
#define DSCR_CMD0_CIM_SYNC 26
#endif /* CONFIG_SOC_AU1200 */
#define AU1550_DSCR_CMD0_UART0_TX 0
#define AU1550_DSCR_CMD0_UART0_RX 1
#define AU1550_DSCR_CMD0_UART3_TX 2
#define AU1550_DSCR_CMD0_UART3_RX 3
#define AU1550_DSCR_CMD0_DMA_REQ0 4
#define AU1550_DSCR_CMD0_DMA_REQ1 5
#define AU1550_DSCR_CMD0_DMA_REQ2 6
#define AU1550_DSCR_CMD0_DMA_REQ3 7
#define AU1550_DSCR_CMD0_USBDEV_RX0 8
#define AU1550_DSCR_CMD0_USBDEV_TX0 9
#define AU1550_DSCR_CMD0_USBDEV_TX1 10
#define AU1550_DSCR_CMD0_USBDEV_TX2 11
#define AU1550_DSCR_CMD0_USBDEV_RX3 12
#define AU1550_DSCR_CMD0_USBDEV_RX4 13
#define AU1550_DSCR_CMD0_PSC0_TX 14
#define AU1550_DSCR_CMD0_PSC0_RX 15
#define AU1550_DSCR_CMD0_PSC1_TX 16
#define AU1550_DSCR_CMD0_PSC1_RX 17
#define AU1550_DSCR_CMD0_PSC2_TX 18
#define AU1550_DSCR_CMD0_PSC2_RX 19
#define AU1550_DSCR_CMD0_PSC3_TX 20
#define AU1550_DSCR_CMD0_PSC3_RX 21
#define AU1550_DSCR_CMD0_PCI_WRITE 22
#define AU1550_DSCR_CMD0_NAND_FLASH 23
#define AU1550_DSCR_CMD0_MAC0_RX 24
#define AU1550_DSCR_CMD0_MAC0_TX 25
#define AU1550_DSCR_CMD0_MAC1_RX 26
#define AU1550_DSCR_CMD0_MAC1_TX 27
#define AU1200_DSCR_CMD0_UART0_TX 0
#define AU1200_DSCR_CMD0_UART0_RX 1
#define AU1200_DSCR_CMD0_UART1_TX 2
#define AU1200_DSCR_CMD0_UART1_RX 3
#define AU1200_DSCR_CMD0_DMA_REQ0 4
#define AU1200_DSCR_CMD0_DMA_REQ1 5
#define AU1200_DSCR_CMD0_MAE_BE 6
#define AU1200_DSCR_CMD0_MAE_FE 7
#define AU1200_DSCR_CMD0_SDMS_TX0 8
#define AU1200_DSCR_CMD0_SDMS_RX0 9
#define AU1200_DSCR_CMD0_SDMS_TX1 10
#define AU1200_DSCR_CMD0_SDMS_RX1 11
#define AU1200_DSCR_CMD0_AES_TX 13
#define AU1200_DSCR_CMD0_AES_RX 12
#define AU1200_DSCR_CMD0_PSC0_TX 14
#define AU1200_DSCR_CMD0_PSC0_RX 15
#define AU1200_DSCR_CMD0_PSC1_TX 16
#define AU1200_DSCR_CMD0_PSC1_RX 17
#define AU1200_DSCR_CMD0_CIM_RXA 18
#define AU1200_DSCR_CMD0_CIM_RXB 19
#define AU1200_DSCR_CMD0_CIM_RXC 20
#define AU1200_DSCR_CMD0_MAE_BOTH 21
#define AU1200_DSCR_CMD0_LCD 22
#define AU1200_DSCR_CMD0_NAND_FLASH 23
#define AU1200_DSCR_CMD0_PSC0_SYNC 24
#define AU1200_DSCR_CMD0_PSC1_SYNC 25
#define AU1200_DSCR_CMD0_CIM_SYNC 26
#define DSCR_CMD0_THROTTLE 30
#define DSCR_CMD0_ALWAYS 31
......
arch/mips/include/asm/mach-db1x00/db1x00.h
View file @ f2e442fd
......@@ -31,10 +31,10 @@
#ifdef CONFIG_MIPS_DB1550
#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
#define DBDMA_AC97_TX_CHAN AU1550_DSCR_CMD0_PSC1_TX
#define DBDMA_AC97_RX_CHAN AU1550_DSCR_CMD0_PSC1_RX
#define DBDMA_I2S_TX_CHAN AU1550_DSCR_CMD0_PSC3_TX
#define DBDMA_I2S_RX_CHAN AU1550_DSCR_CMD0_PSC3_RX
#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR
#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR
......
arch/mips/include/asm/mach-pb1x00/pb1200.h
View file @ f2e442fd
......@@ -28,10 +28,10 @@
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1xxx_psc.h>
#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
#define DBDMA_AC97_TX_CHAN AU1200_DSCR_CMD0_PSC1_TX
#define DBDMA_AC97_RX_CHAN AU1200_DSCR_CMD0_PSC1_RX
#define DBDMA_I2S_TX_CHAN AU1200_DSCR_CMD0_PSC1_TX
#define DBDMA_I2S_RX_CHAN AU1200_DSCR_CMD0_PSC1_RX
/*
* SPI and SMB are muxed on the Pb1200 board.
......
arch/mips/include/asm/mach-pb1x00/pb1550.h
View file @ f2e442fd
......@@ -30,10 +30,10 @@
#include <linux/types.h>
#include <asm/mach-au1x00/au1xxx_psc.h>
#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
#define DBDMA_AC97_TX_CHAN AU1550_DSCR_CMD0_PSC1_TX
#define DBDMA_AC97_RX_CHAN AU1550_DSCR_CMD0_PSC1_RX
#define DBDMA_I2S_TX_CHAN AU1550_DSCR_CMD0_PSC3_TX
#define DBDMA_I2S_RX_CHAN AU1550_DSCR_CMD0_PSC3_RX
#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR
#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR
......
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