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Commit f54bef9e authored by Mark A. Greer's avatar Mark A. Greer Committed by Linus Torvalds
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[PATCH] ppc32: cpci690 updates 

Update the cpci690 platform code:
- pass mem size in from bootwrapper via bi_rec
- some minor fixups
Signed-off-by: default avatarMark A. Greer <mgreer@mvista.com>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent f4c6cc8d
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Showing with 326 additions and 211 deletions
arch/ppc/boot/simple/misc-cpci690.c
View file @ f54bef9e
......@@ -12,16 +12,56 @@
*/
#include <linux/types.h>
#include <asm/io.h>
#include <platforms/cpci690.h>
#define KB (1024UL)
#define MB (1024UL*KB)
#define GB (1024UL*MB)
extern u32 mv64x60_console_baud;
extern u32 mv64x60_mpsc_clk_src;
extern u32 mv64x60_mpsc_clk_freq;
u32 mag = 0xffff;
unsigned long
get_mem_size(void)
{
u32 size;
switch (in_8(((void __iomem *)CPCI690_BR_BASE + CPCI690_BR_MEM_CTLR))
& 0x07) {
case 0x01:
size = 256*MB;
break;
case 0x02:
size = 512*MB;
break;
case 0x03:
size = 768*MB;
break;
case 0x04:
size = 1*GB;
break;
case 0x05:
size = 1*GB + 512*MB;
break;
case 0x06:
size = 2*GB;
break;
default:
size = 0;
}
return size;
}
void
mv64x60_board_init(void __iomem *old_base, void __iomem *new_base)
{
mv64x60_console_baud = CPCI690_MPSC_BAUD;
mv64x60_mpsc_clk_src = CPCI690_MPSC_CLK_SRC;
mv64x60_mpsc_clk_freq = CPCI690_BUS_FREQ;
mv64x60_mpsc_clk_freq =
(get_mem_size() >= (1*GB)) ? 100000000 : 133333333;
}
arch/ppc/configs/cpci690_defconfig
View file @ f54bef9e
This diff is collapsed.
arch/ppc/platforms/cpci690.c
View file @ f54bef9e
......@@ -35,11 +35,7 @@
#define SET_PCI_IDE_NATIVE
static struct mv64x60_handle bh;
static u32 cpci690_br_base;
static const unsigned int cpu_7xx[16] = { /* 7xx & 74xx (but not 745x) */
18, 15, 14, 2, 4, 13, 5, 9, 6, 11, 8, 10, 16, 12, 7, 0
};
static void __iomem *cpci690_br_base;
TODC_ALLOC();
......@@ -55,7 +51,7 @@ cpci690_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
* A B C D
*/
{
{ 90, 91, 88, 89}, /* IDSEL 30/20 - Sentinel */
{ 90, 91, 88, 89 }, /* IDSEL 30/20 - Sentinel */
};
const long min_idsel = 20, max_idsel = 20, irqs_per_slot = 4;
......@@ -67,9 +63,9 @@ cpci690_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
* A B C D
*/
{
{ 93, 94, 95, 92}, /* IDSEL 28/18 - PMC slot 2 */
{ 0, 0, 0, 0}, /* IDSEL 29/19 - Not used */
{ 94, 95, 92, 93}, /* IDSEL 30/20 - PMC slot 1 */
{ 93, 94, 95, 92 }, /* IDSEL 28/18 - PMC slot 2 */
{ 0, 0, 0, 0 }, /* IDSEL 29/19 - Not used */
{ 94, 95, 92, 93 }, /* IDSEL 30/20 - PMC slot 1 */
};
const long min_idsel = 18, max_idsel = 20, irqs_per_slot = 4;
......@@ -77,68 +73,29 @@ cpci690_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
}
}
static int
cpci690_get_cpu_speed(void)
{
unsigned long hid1;
#define GB (1024UL * 1024UL * 1024UL)
hid1 = mfspr(SPRN_HID1) >> 28;
return CPCI690_BUS_FREQ * cpu_7xx[hid1]/2;
static u32
cpci690_get_bus_freq(void)
{
if (boot_mem_size >= (1*GB)) /* bus speed based on mem size */
return 100000000;
else
return 133333333;
}
#define KB (1024UL)
#define MB (1024UL * KB)
#define GB (1024UL * MB)
static const unsigned int cpu_750xx[32] = { /* 750FX & 750GX */
0, 0, 2, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,/* 0-15*/
16, 17, 18, 19, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 0 /*16-31*/
};
unsigned long __init
cpci690_find_end_of_memory(void)
static int
cpci690_get_cpu_freq(void)
{
u32 mem_ctlr_size;
static u32 board_size;
static u8 first_time = 1;
if (first_time) {
/* Using cpci690_set_bat() mapping ==> virt addr == phys addr */
switch (in_8((u8 *) (cpci690_br_base +
CPCI690_BR_MEM_CTLR)) & 0x07) {
case 0x01:
board_size = 256*MB;
break;
case 0x02:
board_size = 512*MB;
break;
case 0x03:
board_size = 768*MB;
break;
case 0x04:
board_size = 1*GB;
break;
case 0x05:
board_size = 1*GB + 512*MB;
break;
case 0x06:
board_size = 2*GB;
break;
default:
board_size = 0xffffffff; /* use mem ctlr size */
} /* switch */
mem_ctlr_size = mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
MV64x60_TYPE_GT64260A);
/* Check that mem ctlr & board reg agree. If not, pick MIN. */
if (board_size != mem_ctlr_size) {
printk(KERN_WARNING "Board register & memory controller"
"mem size disagree (board reg: 0x%lx, "
"mem ctlr: 0x%lx)\n",
(ulong)board_size, (ulong)mem_ctlr_size);
board_size = min(board_size, mem_ctlr_size);
}
first_time = 0;
} /* if */
return board_size;
unsigned long pll_cfg;
pll_cfg = (mfspr(SPRN_HID1) & 0xf8000000) >> 27;
return cpci690_get_bus_freq() * cpu_750xx[pll_cfg]/2;
}
static void __init
......@@ -228,7 +185,7 @@ cpci690_setup_peripherals(void)
mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, CPCI690_BR_BASE,
CPCI690_BR_SIZE, 0);
bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
cpci690_br_base = (u32)ioremap(CPCI690_BR_BASE, CPCI690_BR_SIZE);
cpci690_br_base = ioremap(CPCI690_BR_BASE, CPCI690_BR_SIZE);
mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, CPCI690_TODC_BASE,
CPCI690_TODC_SIZE, 0);
......@@ -329,7 +286,7 @@ cpci690_fixup_mpsc_pdata(struct platform_device *pdev)
pdata->max_idle = 40;
pdata->default_baud = CPCI690_MPSC_BAUD;
pdata->brg_clk_src = CPCI690_MPSC_CLK_SRC;
pdata->brg_clk_freq = CPCI690_BUS_FREQ;
pdata->brg_clk_freq = cpci690_get_bus_freq();
}
static int __init
......@@ -365,7 +322,7 @@ cpci690_reset_board(void)
u32 i = 10000;
local_irq_disable();
out_8((u8 *)(cpci690_br_base + CPCI690_BR_SW_RESET), 0x11);
out_8((cpci690_br_base + CPCI690_BR_SW_RESET), 0x11);
while (i != 0) i++;
panic("restart failed\n");
......@@ -394,10 +351,40 @@ cpci690_power_off(void)
static int
cpci690_show_cpuinfo(struct seq_file *m)
{
char *s;
seq_printf(m, "cpu MHz\t\t: %d\n",
(cpci690_get_cpu_freq() + 500000) / 1000000);
seq_printf(m, "bus MHz\t\t: %d\n",
(cpci690_get_bus_freq() + 500000) / 1000000);
seq_printf(m, "vendor\t\t: " BOARD_VENDOR "\n");
seq_printf(m, "machine\t\t: " BOARD_MACHINE "\n");
seq_printf(m, "cpu MHz\t\t: %d\n", cpci690_get_cpu_speed()/1000/1000);
seq_printf(m, "bus MHz\t\t: %d\n", CPCI690_BUS_FREQ/1000/1000);
seq_printf(m, "FPGA Revision\t: %d\n",
in_8(cpci690_br_base + CPCI690_BR_MEM_CTLR) >> 5);
switch(bh.type) {
case MV64x60_TYPE_GT64260A:
s = "gt64260a";
break;
case MV64x60_TYPE_GT64260B:
s = "gt64260b";
break;
case MV64x60_TYPE_MV64360:
s = "mv64360";
break;
case MV64x60_TYPE_MV64460:
s = "mv64460";
break;
default:
s = "Unknown";
}
seq_printf(m, "bridge type\t: %s\n", s);
seq_printf(m, "bridge rev\t: 0x%x\n", bh.rev);
#if defined(CONFIG_NOT_COHERENT_CACHE)
seq_printf(m, "coherency\t: %s\n", "off");
#else
seq_printf(m, "coherency\t: %s\n", "on");
#endif
return 0;
}
......@@ -407,7 +394,7 @@ cpci690_calibrate_decr(void)
{
ulong freq;
freq = CPCI690_BUS_FREQ / 4;
freq = cpci690_get_bus_freq() / 4;
printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n",
freq/1000000, freq%1000000);
......@@ -416,25 +403,12 @@ cpci690_calibrate_decr(void)
tb_to_us = mulhwu_scale_factor(freq, 1000000);
}
static __inline__ void
cpci690_set_bat(u32 addr, u32 size)
{
addr &= 0xfffe0000;
size &= 0x1ffe0000;
size = ((size >> 17) - 1) << 2;
mb();
mtspr(SPRN_DBAT1U, addr | size | 0x2); /* Vs == 1; Vp == 0 */
mtspr(SPRN_DBAT1L, addr | 0x2a); /* WIMG bits == 0101; PP == r/w access */
mb();
}
#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB_MPSC)
static void __init
cpci690_map_io(void)
{
io_block_mapping(CONFIG_MV64X60_NEW_BASE, CONFIG_MV64X60_NEW_BASE,
128 * KB, _PAGE_IO);
128 * 1024, _PAGE_IO);
}
#endif
......@@ -442,14 +416,15 @@ void __init
platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
#ifdef CONFIG_BLK_DEV_INITRD
initrd_start=initrd_end=0;
initrd_below_start_ok=0;
#endif /* CONFIG_BLK_DEV_INITRD */
parse_bootinfo(find_bootinfo());
loops_per_jiffy = cpci690_get_cpu_speed() / HZ;
#ifdef CONFIG_BLK_DEV_INITRD
/* take care of initrd if we have one */
if (r4) {
initrd_start = r4 + KERNELBASE;
initrd_end = r5 + KERNELBASE;
}
#endif /* CONFIG_BLK_DEV_INITRD */
isa_mem_base = 0;
......@@ -460,7 +435,6 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
ppc_md.restart = cpci690_restart;
ppc_md.power_off = cpci690_power_off;
ppc_md.halt = cpci690_halt;
ppc_md.find_end_of_memory = cpci690_find_end_of_memory;
ppc_md.time_init = todc_time_init;
ppc_md.set_rtc_time = todc_set_rtc_time;
ppc_md.get_rtc_time = todc_get_rtc_time;
......@@ -468,22 +442,13 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
ppc_md.nvram_write_val = todc_direct_write_val;
ppc_md.calibrate_decr = cpci690_calibrate_decr;
/*
* Need to map in board regs (used by cpci690_find_end_of_memory())
* and the bridge's regs (used by progress);
*/
cpci690_set_bat(CPCI690_BR_BASE, 32 * MB);
cpci690_br_base = CPCI690_BR_BASE;
#ifdef CONFIG_SERIAL_TEXT_DEBUG
#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB_MPSC)
ppc_md.setup_io_mappings = cpci690_map_io;
#ifdef CONFIG_SERIAL_TEXT_DEBUG
ppc_md.progress = mv64x60_mpsc_progress;
mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE);
#endif /* CONFIG_SERIAL_TEXT_DEBUG */
#ifdef CONFIG_KGDB
ppc_md.setup_io_mappings = cpci690_map_io;
ppc_md.early_serial_map = cpci690_early_serial_map;
#endif /* CONFIG_KGDB */
#endif /* defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB_MPSC) */
#if defined(CONFIG_SERIAL_MPSC)
platform_notify = cpci690_platform_notify;
......
arch/ppc/platforms/cpci690.h
View file @ f54bef9e
......@@ -73,6 +73,4 @@ typedef struct board_info {
#define CPCI690_MPSC_BAUD 9600
#define CPCI690_MPSC_CLK_SRC 8 /* TCLK */
#define CPCI690_BUS_FREQ 133333333
#endif /* __PPC_PLATFORMS_CPCI690_H */
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