Commit f749f970 authored by Emily Deng's avatar Emily Deng Committed by Greg Kroah-Hartman

drm/amdgpu/sriov:Correct pfvf exchange logic

[ Upstream commit b8cf6618 ]

The pfvf exchange need be in exclusive mode. And add pfvf exchange in gpu
reset.
Signed-off-by: default avatarEmily Deng <Emily.Deng@amd.com>
Reviewed-By: default avatarXiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent bdd8fd8a
...@@ -1653,8 +1653,10 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev) ...@@ -1653,8 +1653,10 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)
amdgpu_amdkfd_device_init(adev); amdgpu_amdkfd_device_init(adev);
if (amdgpu_sriov_vf(adev)) if (amdgpu_sriov_vf(adev)) {
amdgpu_virt_init_data_exchange(adev);
amdgpu_virt_release_full_gpu(adev, true); amdgpu_virt_release_full_gpu(adev, true);
}
return 0; return 0;
} }
...@@ -2555,9 +2557,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, ...@@ -2555,9 +2557,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
goto failed; goto failed;
} }
if (amdgpu_sriov_vf(adev))
amdgpu_virt_init_data_exchange(adev);
amdgpu_fbdev_init(adev); amdgpu_fbdev_init(adev);
r = amdgpu_pm_sysfs_init(adev); r = amdgpu_pm_sysfs_init(adev);
...@@ -3269,6 +3268,7 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device *adev, ...@@ -3269,6 +3268,7 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
r = amdgpu_ib_ring_tests(adev); r = amdgpu_ib_ring_tests(adev);
error: error:
amdgpu_virt_init_data_exchange(adev);
amdgpu_virt_release_full_gpu(adev, true); amdgpu_virt_release_full_gpu(adev, true);
if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) { if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
atomic_inc(&adev->vram_lost_counter); atomic_inc(&adev->vram_lost_counter);
......
...@@ -174,7 +174,7 @@ static int xgpu_ai_send_access_requests(struct amdgpu_device *adev, ...@@ -174,7 +174,7 @@ static int xgpu_ai_send_access_requests(struct amdgpu_device *adev,
return r; return r;
} }
/* Retrieve checksum from mailbox2 */ /* Retrieve checksum from mailbox2 */
if (req == IDH_REQ_GPU_INIT_ACCESS) { if (req == IDH_REQ_GPU_INIT_ACCESS || req == IDH_REQ_GPU_RESET_ACCESS) {
adev->virt.fw_reserve.checksum_key = adev->virt.fw_reserve.checksum_key =
RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2)); mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2));
......
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