Merge bk://bk.arm.linux.org.uk/linux-2.6-rmk

into ppc970.osdl.org:/home/torvalds/v2.6/linux

Documentation/arm/Samsung-S3C24XX/Suspend.txt

@@ -33,7 +33,8 @@ Resuming
   code to resume Linux operation.
 
   GSTATUS4 is currently left alone by the sleep code, and is free to
-  use for any other purposes.
+  use for any other purposes (for example, the EB2410ITX uses this to
+  save memory configuration in).
 
 
 Machine Support
@@ -41,9 +42,9 @@ Machine Support
 
   The machine specific functions must call the s3c2410_pm_init() function
   to say that it's bootloader is capable of resuming. This can be as
-  simple as adding the following to the file:
+  simple as adding the following to the machine's definition:
 
-  late_initcall(s3c2410_pm_init);
+  INITMACHINE(s3c2410_pm_init)
 
   A board can do its own setup before calling s3c2410_pm_init, if it
   needs to setup anything else for power management support.
@@ -52,6 +53,23 @@ Machine Support
   saving the resume address, if your board requires it, then contact
   the maintainer and discuss what is required.
 
+  Note, the origianal method of adding an late_initcall() is wrong,
+  and will end up initialising all compiled machine's pm init!
+
+
+Debugging
+---------
+
+  There are several important things to rember when using PM suspend:
+
+  1) The uart drivers will disable the clocks to the UART blocks when
+     suspending, which means that use of printascii() or similar direct
+     access to the UARTs will cause the debug to stop.
+
+  2) Whilst the pm code itself will attempt to re-enabled the UART clocks,
+     care should be taken that any external clock sources that the UARTs
+     rely on are still enabled at that point
+
 
 Configuration
 -------------

arch/arm/Kconfig

@@ -162,10 +162,10 @@ config ARCH_LH7A40X
 config ARCH_OMAP
 	bool "TI OMAP"
 
-config ARCH_VERSATILE_PB
-	bool "Versatile PB"
+config ARCH_VERSATILE
+	bool "Versatile"
 	help
-	  This enables support for ARM Ltd Versatile PB board.
+	  This enables support for ARM Ltd Versatile board.
 
 config ARCH_IMX
 	bool "IMX"
@@ -205,6 +205,8 @@ source "arch/arm/mach-imx/Kconfig"
 
 source "arch/arm/mach-h720x/Kconfig"
 
+source "arch/arm/mach-versatile/Kconfig"
+
 # Definitions to make life easier
 config ARCH_ACORN
 	bool
@@ -287,9 +289,14 @@ config ICST525
 	depends on ARCH_INTEGRATOR
 	default y
 
+config ICST307
+	bool
+	depends on ARCH_VERSATILE
+	default y
+
 config ARM_AMBA
 	bool
-	depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB
+	depends on ARCH_INTEGRATOR || ARCH_VERSATILE
 	default y
 
 config ISA
@@ -547,7 +554,7 @@ config CMDLINE
 
 config LEDS
 	bool "Timer and CPU usage LEDs"
-	depends on ARCH_NETWINDER || ARCH_EBSA110 || ARCH_EBSA285 || ARCH_SHARK || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_CDB89712 || ARCH_P720T || ARCH_OMAP || ARCH_VERSATILE_PB || ARCH_IMX
+	depends on ARCH_NETWINDER || ARCH_EBSA110 || ARCH_EBSA285 || ARCH_SHARK || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_CDB89712 || ARCH_P720T || ARCH_OMAP || ARCH_VERSATILE || ARCH_IMX
 	help
 	  If you say Y here, the LEDs on your machine will be used
 	  to provide useful information about your current system status.
@@ -560,8 +567,8 @@ config LEDS
 	  system, but the driver will do nothing.
 
 config LEDS_TIMER
-	bool "Timer LED" if LEDS && (ARCH_NETWINDER || ARCH_EBSA285 || ARCH_SHARK || MACH_MAINSTONE || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_P720T || ARCH_VERSATILE_PB || ARCH_IMX)
-	depends on ARCH_NETWINDER || ARCH_EBSA110 || ARCH_EBSA285 || ARCH_SHARK || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_CDB89712 || ARCH_P720T || ARCH_OMAP || ARCH_VERSATILE_PB || ARCH_IMX
+	bool "Timer LED" if LEDS && (ARCH_NETWINDER || ARCH_EBSA285 || ARCH_SHARK || MACH_MAINSTONE || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_P720T || ARCH_VERSATILE || ARCH_IMX)
+	depends on ARCH_NETWINDER || ARCH_EBSA110 || ARCH_EBSA285 || ARCH_SHARK || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_CDB89712 || ARCH_P720T || ARCH_OMAP || ARCH_VERSATILE || ARCH_IMX
 	default y if ARCH_EBSA110
 	help
 	  If you say Y here, one of the system LEDs (the green one on the
@@ -576,7 +583,7 @@ config LEDS_TIMER
 
 config LEDS_CPU
 	bool "CPU usage LED"
-	depends on LEDS && (ARCH_NETWINDER || ARCH_EBSA285 || ARCH_SHARK || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_P720T || ARCH_VERSATILE_PB || ARCH_IMX)
+	depends on LEDS && (ARCH_NETWINDER || ARCH_EBSA285 || ARCH_SHARK || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_P720T || ARCH_VERSATILE || ARCH_IMX)
 	help
 	  If you say Y here, the red LED will be used to give a good real
 	  time indication of CPU usage, by lighting whenever the idle task

arch/arm/Makefile

@@ -93,7 +93,7 @@ textaddr-$(CONFIG_ARCH_FORTUNET)   := 0xc0008000
  machine-$(CONFIG_ARCH_OMAP)	   := omap
  machine-$(CONFIG_ARCH_S3C2410)	   := s3c2410
  machine-$(CONFIG_ARCH_LH7A40X)	   := lh7a40x
- machine-$(CONFIG_ARCH_VERSATILE_PB) := versatile
+ machine-$(CONFIG_ARCH_VERSATILE)  := versatile
  machine-$(CONFIG_ARCH_IMX)	   := imx
  machine-$(CONFIG_ARCH_H720X)	   := h720x
 

arch/arm/common/Makefile

@@ -5,6 +5,7 @@
 obj-y				+= rtctime.o
 obj-$(CONFIG_ARM_AMBA)		+= amba.o
 obj-$(CONFIG_ICST525)		+= icst525.o
+obj-$(CONFIG_ICST307)		+= icst307.o
 obj-$(CONFIG_SA1111)		+= sa1111.o
 obj-$(CONFIG_PCI_HOST_VIA82C505) += via82c505.o
 obj-$(CONFIG_DMABOUNCE)		+= dmabounce.o

arch/arm/common/icst307.c

+/*
+ *  linux/arch/arm/common/icst307.c
+ *
+ *  Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Support functions for calculating clocks/divisors for the ICST307
+ *  clock generators.  See http://www.icst.com/ for more information
+ *  on these devices.
+ *
+ *  This is an almost identical implementation to the ICST525 clock generator.
+ *  The s2div and idx2s files are different
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+
+#include <asm/hardware/icst307.h>
+
+/*
+ * Divisors for each OD setting.
+ */
+static unsigned char s2div[8] = { 10, 2, 8, 4, 5, 7, 3, 6 };
+
+unsigned long icst307_khz(const struct icst307_params *p, struct icst307_vco vco)
+{
+	return p->ref * 2 * (vco.v + 8) / ((vco.r + 2) * s2div[vco.s]);
+}
+
+EXPORT_SYMBOL(icst307_khz);
+
+/*
+ * Ascending divisor S values.
+ */
+static unsigned char idx2s[8] = { 1, 6, 3, 4, 7, 5, 2, 0 };
+
+struct icst307_vco
+icst307_khz_to_vco(const struct icst307_params *p, unsigned long freq)
+{
+	struct icst307_vco vco = { .s = 1, .v = p->vd_max, .r = p->rd_max };
+	unsigned long f;
+	unsigned int i = 0, rd, best = (unsigned int)-1;
+
+	/*
+	 * First, find the PLL output divisor such
+	 * that the PLL output is within spec.
+	 */
+	do {
+		f = freq * s2div[idx2s[i]];
+
+		/*
+		 * f must be between 6MHz and 200MHz (3.3 or 5V)
+		 */
+		if (f > 6000 && f <= p->vco_max)
+			break;
+	} while (i < ARRAY_SIZE(idx2s));
+
+	if (i > ARRAY_SIZE(idx2s))
+		return vco;
+
+	vco.s = idx2s[i];
+
+	/*
+	 * Now find the closest divisor combination
+	 * which gives a PLL output of 'f'.
+	 */
+	for (rd = p->rd_min; rd <= p->rd_max; rd++) {
+		unsigned long fref_div, f_pll;
+		unsigned int vd;
+		int f_diff;
+
+		fref_div = (2 * p->ref) / rd;
+
+		vd = (f + fref_div / 2) / fref_div;
+		if (vd < p->vd_min || vd > p->vd_max)
+			continue;
+
+		f_pll = fref_div * vd;
+		f_diff = f_pll - f;
+		if (f_diff < 0)
+			f_diff = -f_diff;
+
+		if ((unsigned)f_diff < best) {
+			vco.v = vd - 8;
+			vco.r = rd - 2;
+			if (f_diff == 0)
+				break;
+			best = f_diff;
+		}
+	}
+
+	return vco;
+}
+
+EXPORT_SYMBOL(icst307_khz_to_vco);
+
+struct icst307_vco
+icst307_ps_to_vco(const struct icst307_params *p, unsigned long period)
+{
+	struct icst307_vco vco = { .s = 1, .v = p->vd_max, .r = p->rd_max };
+	unsigned long f, ps;
+	unsigned int i = 0, rd, best = (unsigned int)-1;
+
+	ps = 1000000000UL / p->vco_max;
+
+	/*
+	 * First, find the PLL output divisor such
+	 * that the PLL output is within spec.
+	 */
+	do {
+		f = period / s2div[idx2s[i]];
+
+		/*
+		 * f must be between 6MHz and 200MHz (3.3 or 5V)
+		 */
+		if (f >= ps && f < 1000000000UL / 6000 + 1)
+			break;
+	} while (i < ARRAY_SIZE(idx2s));
+
+	if (i > ARRAY_SIZE(idx2s))
+		return vco;
+
+	vco.s = idx2s[i];
+
+	ps = 500000000UL / p->ref;
+
+	/*
+	 * Now find the closest divisor combination
+	 * which gives a PLL output of 'f'.
+	 */
+	for (rd = p->rd_min; rd <= p->rd_max; rd++) {
+		unsigned long f_in_div, f_pll;
+		unsigned int vd;
+		int f_diff;
+
+		f_in_div = ps * rd;
+
+		vd = (f_in_div + f / 2) / f;
+		if (vd < p->vd_min || vd > p->vd_max)
+			continue;
+
+		f_pll = (f_in_div + vd / 2) / vd;
+		f_diff = f_pll - f;
+		if (f_diff < 0)
+			f_diff = -f_diff;
+
+		if ((unsigned)f_diff < best) {
+			vco.v = vd - 8;
+			vco.r = rd - 2;
+			if (f_diff == 0)
+				break;
+			best = f_diff;
+		}
+	}
+
+	return vco;
+}
+
+EXPORT_SYMBOL(icst307_ps_to_vco);

arch/arm/common/locomo.c

@@ -609,17 +609,15 @@ static void __locomo_remove(struct locomo *lchip)
 static int locomo_probe(struct device *dev)
 {
 	struct platform_device *pdev = to_platform_device(dev);
-	struct resource *mem = NULL, *irq = NULL;
-	int i;
-
-	for (i = 0; i < pdev->num_resources; i++) {
-		if (pdev->resource[i].flags & IORESOURCE_MEM)
-			mem = &pdev->resource[i];
-		if (pdev->resource[i].flags & IORESOURCE_IRQ)
-			irq = &pdev->resource[i];
-	}
+	struct resource *mem;
+	int irq;
+
+	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!mem)
+		return -EINVAL;
+	irq = platform_get_irq(pdev, 0);
 
-	return __locomo_probe(dev, mem, irq ? irq->start : NO_IRQ);
+	return __locomo_probe(dev, mem, irq);
 }
 
 static int locomo_remove(struct device *dev)
@@ -756,7 +754,7 @@ module_exit(locomo_exit);
 
 MODULE_DESCRIPTION("Sharp LoCoMo core driver");
 MODULE_LICENSE("GPL");
-MODULE_AUTHOR("John Lenz <jelenz@students.wisc.edu>");
+MODULE_AUTHOR("John Lenz <lenz@cs.wisc.edu>");
 
 EXPORT_SYMBOL(locomo_driver_register);
 EXPORT_SYMBOL(locomo_driver_unregister);

arch/arm/kernel/debug.S

@@ -647,7 +647,7 @@
 		.endm
 
 
-#elif defined(CONFIG_ARCH_VERSATILE_PB)
+#elif defined(CONFIG_ARCH_VERSATILE)
 
 #include <asm/hardware/amba_serial.h>
 

arch/arm/kernel/entry-armv.S

@@ -464,7 +464,7 @@ ENTRY(soft_irq_mask)
 		.macro	irq_prio_table
 		.endm
 
-#elif defined(CONFIG_ARCH_VERSATILE_PB)
+#elif defined(CONFIG_ARCH_VERSATILE)
 
 		.macro	disable_fiq
 		.endm

arch/arm/lib/csumpartial.S

@@ -73,8 +73,7 @@ td3	.req	lr
 .done:		adc	r0, sum, #0		@ collect up the last carry
 		ldr	td0, [sp], #4
 		tst	td0, #1			@ check buffer alignment
-		movne	td0, r0, lsl #8		@ rotate checksum by 8 bits
-		orrne	r0, td0, r0, lsr #24
+		movne	r0, r0, ror #8		@ rotate checksum by 8 bits
 		ldr	pc, [sp], #4		@ return
 
 .not_aligned:	tst	buf, #1			@ odd address

arch/arm/lib/csumpartialcopygeneric.S

@@ -160,8 +160,7 @@ FN_ENTRY
 .done:		adc	r0, sum, #0
 		ldr	sum, [sp, #0]		@ dst
 		tst	sum, #1
-		movne	sum, r0, lsl #8
-		orrne	r0, sum, r0, lsr #24
+		movne	r0, r0, ror #8
 		load_regs	ea
 
 .src_not_aligned:

arch/arm/lib/io-readsl.S

@@ -27,11 +27,10 @@ ENTRY(__raw_readsl)
 		stmia	r1!, {r3, r4, ip, lr}
 		bpl	1b
 		ldmfd	sp!, {r4, lr}
-2:		tst	r2, #2
-		ldrne	r3, [r0, #0]
-		ldrne	ip, [r0, #0]
-		stmneia	r1!, {r3, ip}
-		tst	r2, #1
+2:		movs	r2, r2, lsl #31
+		ldrcs	r3, [r0, #0]
+		ldrcs	ip, [r0, #0]
+		stmcsia	r1!, {r3, ip}
 		ldrne	r3, [r0, #0]
 		strne	r3, [r1, #0]
 		mov	pc, lr

arch/arm/lib/io-writesl.S

@@ -27,12 +27,11 @@ ENTRY(__raw_writesl)
 		str	lr, [r0, #0]
 		bpl	1b
 		ldmfd	sp!, {r4, lr}
-2:		tst	r2, #2
-		ldmneia	r1!, {r3, ip}
-		strne	r3, [r0, #0]
-		strne	ip, [r0, #0]
-		tst	r2, #1
+2:		movs	r2, r2, lsl #31
+		ldmcsia	r1!, {r3, ip}
+		strcs	r3, [r0, #0]
 		ldrne	r3, [r1, #0]
+		strcs	ip, [r0, #0]
 		strne	r3, [r0, #0]
 		mov	pc, lr
 

arch/arm/mach-ixp4xx/common.c

@@ -261,7 +261,7 @@ static void __init ixp4xx_timer_init(void)
 	setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq);
 }
 
-struct ixp4xx_timer = {
+struct sys_timer ixp4xx_timer = {
 	.init		= ixp4xx_timer_init,
 	.offset		= ixp4xx_gettimeoffset,
 };

arch/arm/mach-omap/Kconfig

+if ARCH_OMAP
 
 menu "TI OMAP Implementations"
 
@@ -171,3 +172,5 @@ config OMAP_ARM_30MHZ
           Enable 30MHz clock for OMAP CPU. If unsure, say N.
 
 endmenu
+
+endif

arch/arm/mach-omap/clock.h

@@ -48,8 +48,8 @@ struct mpu_rate {
 #define VIRTUAL_CLOCK		8
 #define ALWAYS_ENABLED		16
 #define ENABLE_REG_32BIT	32
-#define DOES_NOT_EXIST_ON_1510	64
-#define DOES_NOT_EXIST_ON_1610	128 /* Including 1710 */
+#define CLOCK_IN_OMAP16XX	64
+#define CLOCK_IN_OMAP1510	128
 
 /* ARM_CKCTL bit shifts */
 #define CKCTL_PERDIV_OFFSET	0

arch/arm/mach-omap/common.c

@@ -17,6 +17,7 @@
 #include <linux/serial.h>
 #include <linux/tty.h>
 #include <linux/serial_core.h>
+#include <linux/serial_reg.h>
 
 #include <asm/hardware.h>
 #include <asm/system.h>
@@ -306,39 +307,66 @@ void omap_map_io(void)
 		_omap_map_io();
 }
 
+static inline unsigned int omap_serial_in(struct uart_port *up, int offset)
+{
+	offset <<= up->regshift;
+	return (unsigned int)__raw_readb(up->membase + offset);
+}
+
+static inline void omap_serial_outp(struct uart_port *up, int offset, int value)
+{
+	offset <<= up->regshift;
+	__raw_writeb(value, up->membase + offset);
+}
+
+/*
+ * Internal UARTs need to be initialized for the 8250 autoconfig to work
+ * properly.
+ */
+static void __init omap_serial_reset(struct uart_port *up)
+{
+	omap_serial_outp(up, UART_OMAP_MDR1, 0x07); /* disable UART */
+	omap_serial_outp(up, UART_OMAP_MDR1, 0x00); /* enable UART */
+
+	if (!cpu_is_omap1510()) {
+		omap_serial_outp(up, UART_OMAP_SYSC, 0x01);
+		while (!(omap_serial_in(up, UART_OMAP_SYSC) & 0x01));
+	}
+}
+
 static struct uart_port omap_serial_ports[] = {
 	{
 		.membase	= (char*)IO_ADDRESS(OMAP_UART1_BASE),
 		.mapbase	= (unsigned long)OMAP_UART1_BASE,
 		.irq		= INT_UART1,
-		.flags		= UPF_SKIP_TEST,
+		.flags		= UPF_BOOT_AUTOCONF,
 		.iotype		= UPIO_MEM,
 		.regshift	= 2,
 		.uartclk	= OMAP16XX_BASE_BAUD * 16,
 		.line		= 0,
-		.type		= PORT_OMAP,
+		.type		= PORT_16654,
 		.fifosize	= 64
 	} , {
 		.membase	= (char*)IO_ADDRESS(OMAP_UART2_BASE),
 		.mapbase	= (unsigned long)OMAP_UART2_BASE,
 		.irq		= INT_UART2,
-		.flags		= UPF_SKIP_TEST,
+		.flags		= UPF_BOOT_AUTOCONF,
 		.iotype		= UPIO_MEM,
 		.regshift	= 2,
 		.uartclk	= OMAP16XX_BASE_BAUD * 16,
 		.line		= 1,
-		.type		= PORT_OMAP,
+		.type		= PORT_16654,
 		.fifosize	= 64
 	} , {
 		.membase	= (char*)IO_ADDRESS(OMAP_UART3_BASE),
 		.mapbase	= (unsigned long)OMAP_UART3_BASE,
 		.irq		= INT_UART3,
-		.flags		= UPF_SKIP_TEST,
+		.flags		= UPF_BOOT_AUTOCONF,
 		.iotype		= UPIO_MEM,
 		.regshift	= 2,
 		.uartclk	= OMAP16XX_BASE_BAUD * 16,
 		.line		= 2,
-		.type		= PORT_OMAP,
+		.type		= PORT_16654,
 		.fifosize	= 64
 	}
 };
@@ -366,8 +394,6 @@ void __init omap_serial_init(int ports[OMAP_MAX_NR_PORTS])
 	}
 
 	for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
-		unsigned long port;
-		unsigned char regshift;
 		unsigned char reg;
 
 		if (ports[i] != 1)
@@ -382,7 +408,7 @@ void __init omap_serial_init(int ports[OMAP_MAX_NR_PORTS])
 					reg = fpga_read(OMAP1510_FPGA_POWER);
 					reg |= OMAP1510_FPGA_PCR_COM1_EN;
 					fpga_write(reg, OMAP1510_FPGA_POWER);
-					udelay(1);
+					udelay(10);
 				}
 			}
 			break;
@@ -394,7 +420,7 @@ void __init omap_serial_init(int ports[OMAP_MAX_NR_PORTS])
 					reg = fpga_read(OMAP1510_FPGA_POWER);
 					reg |= OMAP1510_FPGA_PCR_COM2_EN;
 					fpga_write(reg, OMAP1510_FPGA_POWER);
-					udelay(1);
+					udelay(10);
 				}
 			}
 			break;
@@ -405,16 +431,8 @@ void __init omap_serial_init(int ports[OMAP_MAX_NR_PORTS])
 			}
 			break;
 		}
-
-		/* Reset port */
-		if (!cpu_is_omap1510()) {
-			port = (unsigned long)omap_serial_ports[i].membase;
-			regshift = omap_serial_ports[i].regshift;
-			writeb(0x01, port + (UART_SYSC << regshift));
-			while (!(readb(port + (UART_SYSC << regshift)) & 0x01));
-		}
-
-		//early_serial_setup(&omap_serial_ports[i]);
+		omap_serial_reset(&omap_serial_ports[i]);
+		early_serial_setup(&omap_serial_ports[i]);
 	}
 }
 

arch/arm/mach-pxa/ssp.c

@@ -185,7 +185,7 @@ int ssp_init(struct ssp_dev *dev, u32 port, u32 mode, u32 flags, u32 psp_flags,
 {
 	int ret, irq;
 
-	if (!request_mem_region(__PREG(SSCR0_P(dev->port)), 0x2c, "SSP")) {
+	if (!request_mem_region(__PREG(SSCR0_P(port)), 0x2c, "SSP")) {
 		return -EBUSY;
 	}
 

arch/arm/mach-s3c2410/cpu.c

@@ -66,7 +66,7 @@ static struct cpu_table cpu_ids[] __initdata = {
 		.name   = name_s3c2410
 	},
 	{
-		.idcode	= 0x3241002,
+		.idcode	= 0x32410002,
 		.idmask = 0xffffffff,
 		.map_io = s3c2410_map_io,
 		.init   = s3c2410_init,

arch/arm/mach-s3c2410/gpio.c

@@ -28,6 +28,7 @@
  *	01-Oct-2004  BJD  Fixed mask bug in pullup() call
  *	01-Oct-2004  BJD  Added getirq() to turn pin into irqno
  *	04-Oct-2004  BJD  Added irq filter controls for GPIO
+ *	05-Nov-2004  BJD  EXPORT_SYMBOL() added for all code
  */
 
 
@@ -66,6 +67,8 @@ void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function)
 	local_irq_restore(flags);
 }
 
+EXPORT_SYMBOL(s3c2410_gpio_cfgpin);
+
 unsigned int s3c2410_gpio_getcfg(unsigned int pin)
 {
 	unsigned long base = S3C2410_GPIO_BASE(pin);
@@ -80,6 +83,8 @@ unsigned int s3c2410_gpio_getcfg(unsigned int pin)
 	return __raw_readl(base) & mask;
 }
 
+EXPORT_SYMBOL(s3c2410_gpio_getcfg);
+
 void s3c2410_gpio_pullup(unsigned int pin, unsigned int to)
 {
 	unsigned long base = S3C2410_GPIO_BASE(pin);
@@ -100,6 +105,8 @@ void s3c2410_gpio_pullup(unsigned int pin, unsigned int to)
 	local_irq_restore(flags);
 }
 
+EXPORT_SYMBOL(s3c2410_gpio_pullup);
+
 void s3c2410_gpio_setpin(unsigned int pin, unsigned int to)
 {
 	unsigned long base = S3C2410_GPIO_BASE(pin);
@@ -117,6 +124,8 @@ void s3c2410_gpio_setpin(unsigned int pin, unsigned int to)
 	local_irq_restore(flags);
 }
 
+EXPORT_SYMBOL(s3c2410_gpio_setpin);
+
 unsigned int s3c2410_gpio_getpin(unsigned int pin)
 {
 	unsigned long base = S3C2410_GPIO_BASE(pin);
@@ -125,6 +134,8 @@ unsigned int s3c2410_gpio_getpin(unsigned int pin)
 	return __raw_readl(base + 0x04) & (1<< offs);
 }
 
+EXPORT_SYMBOL(s3c2410_gpio_getpin);
+
 unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
 {
 	unsigned long flags;
@@ -140,6 +151,8 @@ unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
 	return misccr;
 }
 
+EXPORT_SYMBOL(s3c2410_modify_misccr);
+
 int s3c2410_gpio_getirq(unsigned int pin)
 {
 	if (pin < S3C2410_GPF0 || pin > S3C2410_GPG15_EINT23)
@@ -157,6 +170,8 @@ int s3c2410_gpio_getirq(unsigned int pin)
 	return (pin - S3C2410_GPG0) + IRQ_EINT8;
 }
 
+EXPORT_SYMBOL(s3c2410_gpio_getirq);
+
 int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
 			   unsigned int config)
 {
@@ -192,3 +207,5 @@ int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
 
 	return 0;
 }
+
+EXPORT_SYMBOL(s3c2410_gpio_irqfilter);

arch/arm/mach-s3c2410/irq.c

@@ -36,6 +36,9 @@
  *
  *   05-Oct-2004  Ben Dooks <ben@simtec.co.uk>
  *		  Add support for power management controls
+ *
+ *   04-Nov-2004  Ben Dooks
+ *		  Fix standard IRQ wake for EINT0..4 and RTC
 */
 
 #include <linux/init.h>
@@ -91,7 +94,7 @@ s3c_irq_wake(unsigned int irqno, unsigned int state)
 	if (!state)
 		s3c_irqwake_intmask |= irqbit;
 	else
-		s3c_irqwake_intmask &= irqbit;
+		s3c_irqwake_intmask &= ~irqbit;
 
 	return 0;
 }

arch/arm/mach-s3c2410/pm.c

@@ -23,6 +23,7 @@
  *
  * Parts based on arch/arm/mach-pxa/pm.c
  *
+ * Thanks to Dimitry Andric for debugging
 */
 
 #include <linux/config.h>
@@ -33,10 +34,12 @@
 #include <linux/interrupt.h>
 #include <linux/crc32.h>
 #include <linux/ioport.h>
+#include <linux/delay.h>
 
 #include <asm/hardware.h>
 #include <asm/io.h>
 
+#include <asm/arch/regs-serial.h>
 #include <asm/arch/regs-clock.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-mem.h>
@@ -68,7 +71,21 @@ struct sleep_save {
 
 static struct sleep_save core_save[] = {
 	SAVE_ITEM(S3C2410_LOCKTIME),
-	SAVE_ITEM(S3C2410_CLKCON)
+	SAVE_ITEM(S3C2410_CLKCON),
+
+	/* we restore the timings here, with the proviso that the board
+	 * brings the system up in an slower, or equal frequency setting
+	 * to the original system.
+	 *
+	 * if we cannot guarantee this, then things are going to go very
+	 * wrong here, as we modify the refresh and both pll settings.
+	 */
+
+	SAVE_ITEM(S3C2410_REFRESH),
+	SAVE_ITEM(S3C2410_MPLLCON),
+	SAVE_ITEM(S3C2410_UPLLCON),
+	SAVE_ITEM(S3C2410_CLKDIVN),
+	SAVE_ITEM(S3C2410_CLKSLOW),
 };
 
 /* this lot should be really saved by the IRQ code */
@@ -115,6 +132,20 @@ static struct sleep_save gpio_save[] = {
 };
 
 #ifdef CONFIG_S3C2410_PM_DEBUG
+
+#define SAVE_UART(va) \
+	SAVE_ITEM((va) + S3C2410_ULCON), \
+	SAVE_ITEM((va) + S3C2410_UCON), \
+	SAVE_ITEM((va) + S3C2410_UFCON), \
+	SAVE_ITEM((va) + S3C2410_UMCON), \
+	SAVE_ITEM((va) + S3C2410_UBRDIV)
+
+static struct sleep_save uart_save[] = {
+	SAVE_UART(S3C2410_VA_UART0),
+	SAVE_UART(S3C2410_VA_UART1),
+	SAVE_UART(S3C2410_VA_UART2),
+};
+
 /* debug
  *
  * we send the debug to printascii() to allow it to be seen if the
@@ -135,10 +166,24 @@ static void pm_dbg(const char *fmt, ...)
 	printascii(buff);
 }
 
+static void s3c2410_pm_debug_init(void)
+{
+	unsigned long tmp = __raw_readl(S3C2410_CLKCON);
+
+	/* re-start uart clocks */
+	tmp |= S3C2410_CLKCON_UART0;
+	tmp |= S3C2410_CLKCON_UART1;
+	tmp |= S3C2410_CLKCON_UART2;
+
+	__raw_writel(tmp, S3C2410_CLKCON);
+	udelay(10);
+}
 
 #define DBG(fmt...) pm_dbg(fmt)
 #else
 #define DBG(fmt...) printk(KERN_DEBUG fmt)
+
+#define s3c2410_pm_debug_init() do { } while(0)
 #endif
 
 #if defined(CONFIG_S3C2410_PM_CHECK) && CONFIG_S3C2410_PM_CHECK_CHUNKSIZE != 0
@@ -329,6 +374,9 @@ static void s3c2410_pm_check_restore(void)
 }
 
 #else
+
+static struct sleep_save uart_save[] = {};
+
 #define s3c2410_pm_check_prepare() do { } while(0)
 #define s3c2410_pm_check_restore() do { } while(0)
 #define s3c2410_pm_check_store()   do { } while(0)
@@ -344,12 +392,20 @@ static void s3c2410_pm_do_save(struct sleep_save *ptr, int count)
 	}
 }
 
+/* s3c2410_pm_do_restore
+ *
+ * restore the system from the given list of saved registers
+ *
+ * Note, we do not use DBG() in here, as the system may not have
+ * restore the UARTs state yet
+*/
 
 static void s3c2410_pm_do_restore(struct sleep_save *ptr, int count)
 {
 	for (; count > 0; count--, ptr++) {
-		DBG("restore %08lx (restore %08lx, current %08x)\n",
-		    ptr->reg, ptr->val, __raw_readl(ptr->reg));
+		printk(KERN_DEBUG "restore %08lx (restore %08lx, was %08x)\n",
+		       ptr->reg, ptr->val, __raw_readl(ptr->reg));
+
 		__raw_writel(ptr->val, ptr->reg);
 	}
 }
@@ -434,11 +490,15 @@ static void s3c2410_pm_configure_extint(void)
  * central control for sleep/resume process
 */
 
-static int s3c2410_pm_enter(u32 state)
+static int s3c2410_pm_enter(suspend_state_t state)
 {
 	unsigned long regs_save[16];
 	unsigned long tmp;
 
+	/* ensure the debug is initialised (if enabled) */
+
+	s3c2410_pm_debug_init();
+
 	DBG("s3c2410_pm_enter(%d)\n", state);
 
 	if (state != PM_SUSPEND_MEM) {
@@ -480,6 +540,7 @@ static int s3c2410_pm_enter(u32 state)
 	s3c2410_pm_do_save(gpio_save, ARRAY_SIZE(gpio_save));
 	s3c2410_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
 	s3c2410_pm_do_save(core_save, ARRAY_SIZE(core_save));
+	s3c2410_pm_do_save(uart_save, ARRAY_SIZE(uart_save));
 
 	/* set the irq configuration for wake */
 
@@ -493,7 +554,7 @@ static int s3c2410_pm_enter(u32 state)
 
 	/* ack any outstanding external interrupts before we go to sleep */
 
-	__raw_writel(S3C2410_EINTPEND, __raw_readl(S3C2410_EINTPEND));
+	__raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND);
 
 	/* flush cache back to ram */
 
@@ -512,9 +573,18 @@ static int s3c2410_pm_enter(u32 state)
 	/* unset the return-from-sleep flag, to ensure reset */
 
 	tmp = __raw_readl(S3C2410_GSTATUS2);
-	tmp &= S3C2410_GSTATUs2_OFFRESET;
+	tmp &= S3C2410_GSTATUS2_OFFRESET;
 	__raw_writel(tmp, S3C2410_GSTATUS2);
 
+	/* restore the system state */
+
+	s3c2410_pm_do_restore(core_save, ARRAY_SIZE(core_save));
+	s3c2410_pm_do_restore(gpio_save, ARRAY_SIZE(gpio_save));
+	s3c2410_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
+	s3c2410_pm_do_restore(uart_save, ARRAY_SIZE(uart_save));
+
+	s3c2410_pm_debug_init();
+
 	/* check what irq (if any) restored the system */
 
 	DBG("post sleep: IRQs 0x%08x, 0x%08x\n",
@@ -527,12 +597,6 @@ static int s3c2410_pm_enter(u32 state)
 	s3c2410_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND),
 				    s3c_irqwake_eintmask);
 
-	DBG("post sleep, restoring state...\n");
-
-	s3c2410_pm_do_restore(core_save, ARRAY_SIZE(core_save));
-	s3c2410_pm_do_restore(gpio_save, ARRAY_SIZE(gpio_save));
-	s3c2410_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
-
 	DBG("post sleep, preparing to return\n");
 
 	s3c2410_pm_check_restore();
@@ -546,7 +610,7 @@ static int s3c2410_pm_enter(u32 state)
 /*
  * Called after processes are frozen, but before we shut down devices.
  */
-static int s3c2410_pm_prepare(u32 state)
+static int s3c2410_pm_prepare(suspend_state_t state)
 {
 	return 0;
 }
@@ -554,7 +618,7 @@ static int s3c2410_pm_prepare(u32 state)
 /*
  * Called after devices are re-setup, but before processes are thawed.
  */
-static int s3c2410_pm_finish(u32 state)
+static int s3c2410_pm_finish(suspend_state_t state)
 {
 	return 0;
 }

arch/arm/mach-s3c2410/sleep.S

@@ -35,7 +35,10 @@
 #include <asm/arch/regs-mem.h>
 #include <asm/arch/regs-serial.h>
 
-#define CONFIG_DEBUG_RESUME
+/* CONFIG_DEBUG_RESUME is dangerous if your bootloader does not
+ * reset the UART configuration, only enable if you really need this!
+*/
+//#define CONFIG_DEBUG_RESUME
 
 	.text
 
@@ -133,6 +136,15 @@ ENTRY(s3c2410_cpu_resume)
 	mov	r2, #S3C2410_PA_UART & 0xff000000
 	orr	r2, r2, #S3C2410_PA_UART & 0xff000
 
+#if 0
+	/* SMDK2440 LED set */
+	mov	r14, #S3C2410_PA_GPIO
+	ldr	r12, [ r14, #0x54 ]
+	bic	r12, r12, #3<<4
+	orr	r12, r12, #1<<7
+	str	r12, [ r14, #0x54 ]
+#endif
+
 #ifdef CONFIG_DEBUG_RESUME
 	mov	r3, #'L'
 	strb	r3, [ r2, #S3C2410_UTXH ]

arch/arm/mach-sa1100/generic.c

@@ -161,7 +161,7 @@ static u64 sa11x0udc_dma_mask = 0xffffffffUL;
 
 static struct platform_device sa11x0udc_device = {
 	.name		= "sa11x0-udc",
-	.id		= 0,
+	.id		= -1,
 	.dev		= {
 		.dma_mask = &sa11x0udc_dma_mask,
 		.coherent_dma_mask = 0xffffffff,
@@ -212,7 +212,7 @@ static u64 sa11x0mcp_dma_mask = 0xffffffffUL;
 
 static struct platform_device sa11x0mcp_device = {
 	.name		= "sa11x0-mcp",
-	.id		= 0,
+	.id		= -1,
 	.dev = {
 		.dma_mask = &sa11x0mcp_dma_mask,
 		.coherent_dma_mask = 0xffffffff,
@@ -233,7 +233,7 @@ static u64 sa11x0ssp_dma_mask = 0xffffffffUL;
 
 static struct platform_device sa11x0ssp_device = {
 	.name		= "sa11x0-ssp",
-	.id		= 0,
+	.id		= -1,
 	.dev = {
 		.dma_mask = &sa11x0ssp_dma_mask,
 		.coherent_dma_mask = 0xffffffff,
@@ -257,7 +257,7 @@ static struct resource sa11x0fb_resources[] = {
 
 static struct platform_device sa11x0fb_device = {
 	.name		= "sa11x0-fb",
-	.id		= 0,
+	.id		= -1,
 	.dev = {
 		.coherent_dma_mask = 0xffffffff,
 	},
@@ -267,7 +267,7 @@ static struct platform_device sa11x0fb_device = {
 
 static struct platform_device sa11x0pcmcia_device = {
 	.name		= "sa11x0-pcmcia",
-	.id		= 0,
+	.id		= -1,
 };
 
 static struct platform_device *sa11x0_devices[] __initdata = {

arch/arm/mach-versatile/Kconfig

+menu "Versatile platform type"
+	depends on ARCH_VERSATILE
+
+config ARCH_VERSATILE_PB
+	bool "Support Versatile/PB platform"
+	default y
+	help
+	  Include support for the ARM(R) Versatile/PB platform.
+
+config ARCH_VERSATILE_AB
+	bool "Support Versatile/AB platform"
+	default n
+	help
+	  Include support for the ARM(R) Versatile/AP platform.
+
+endmenu

arch/arm/mach-versatile/Makefile

@@ -3,3 +3,5 @@
 #
 
 obj-y					:= core.o clock.o
+obj-$(CONFIG_ARCH_VERSATILE_PB)		+= versatile_pb.o
+obj-$(CONFIG_ARCH_VERSATILE_AB)		+= versatile_ab.o

arch/arm/mach-versatile/clock.c

@@ -16,7 +16,7 @@
 
 #include <asm/semaphore.h>
 #include <asm/hardware/clock.h>
-#include <asm/hardware/icst525.h>
+#include <asm/hardware/icst307.h>
 
 #include "clock.h"
 
@@ -83,12 +83,12 @@ EXPORT_SYMBOL(clk_round_rate);
 int clk_set_rate(struct clk *clk, unsigned long rate)
 {
 	int ret = -EIO;
-#if 0 // Not yet
+
 	if (clk->setvco) {
-		struct icst525_vco vco;
+		struct icst307_vco vco;
 
-		vco = icst525_khz_to_vco(clk->params, rate / 1000);
-		clk->rate = icst525_khz(clk->params, vco) * 1000;
+		vco = icst307_khz_to_vco(clk->params, rate / 1000);
+		clk->rate = icst307_khz(clk->params, vco) * 1000;
 
 		printk("Clock %s: setting VCO reg params: S=%d R=%d V=%d\n",
 			clk->name, vco.s, vco.r, vco.v);
@@ -96,7 +96,6 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
 		clk->setvco(clk, vco);
 		ret = 0;
 	}
-#endif
 	return ret;
 }
 EXPORT_SYMBOL(clk_set_rate);

arch/arm/mach-versatile/clock.h

@@ -9,16 +9,16 @@
  * published by the Free Software Foundation.
  */
 struct module;
-struct icst525_params;
+struct icst307_params;
 
 struct clk {
 	struct list_head	node;
 	unsigned long		rate;
 	struct module		*owner;
 	const char		*name;
-	const struct icst525_params *params;
+	const struct icst307_params *params;
 	void			*data;
-	void			(*setvco)(struct clk *, struct icst525_vco vco);
+	void			(*setvco)(struct clk *, struct icst307_vco vco);
 };
 
 int clk_register(struct clk *clk);

arch/arm/mach-versatile/core.h

+/*
+ *  linux/arch/arm/mach-versatile/core.h
+ *
+ *  Copyright (C) 2004 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_VERSATILE_H
+#define __ASM_ARCH_VERSATILE_H
+
+#include <asm/hardware/amba.h>
+
+extern void __init versatile_init(void);
+extern void __init versatile_init_irq(void);
+extern void __init versatile_map_io(void);
+extern struct sys_timer versatile_timer;
+extern unsigned int mmc_status(struct device *dev);
+
+#define AMBA_DEVICE(name,busid,base,plat)			\
+static struct amba_device name##_device = {			\
+	.dev		= {					\
+		.coherent_dma_mask = ~0,			\
+		.bus_id	= busid,				\
+		.platform_data = plat,				\
+	},							\
+	.res		= {					\
+		.start	= VERSATILE_##base##_BASE,		\
+		.end	= (VERSATILE_##base##_BASE) + SZ_4K - 1,\
+		.flags	= IORESOURCE_MEM,			\
+	},							\
+	.dma_mask	= ~0,					\
+	.irq		= base##_IRQ,				\
+	/* .dma		= base##_DMA,*/				\
+}
+
+#endif

arch/arm/mach-versatile/versatile_ab.c

+/*
+ *  linux/arch/arm/mach-versatile/versatile_ab.c
+ *
+ *  Copyright (C) 2004 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/sysdev.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+#include <asm/hardware/amba.h>
+
+#include <asm/mach/arch.h>
+
+#include "core.h"
+
+MACHINE_START(VERSATILE_AB, "ARM-Versatile AB")
+	MAINTAINER("ARM Ltd/Deep Blue Solutions Ltd")
+	BOOT_MEM(0x00000000, 0x101f1000, 0xf11f1000)
+	BOOT_PARAMS(0x00000100)
+	MAPIO(versatile_map_io)
+	INITIRQ(versatile_init_irq)
+	.timer		= &versatile_timer,
+	INIT_MACHINE(versatile_init)
+MACHINE_END

arch/arm/mach-versatile/versatile_pb.c

+/*
+ *  linux/arch/arm/mach-versatile/versatile_pb.c
+ *
+ *  Copyright (C) 2004 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/sysdev.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+#include <asm/hardware/amba.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/mmc.h>
+
+#include "core.h"
+
+#if 1
+#define IRQ_MMCI1A	IRQ_VICSOURCE23
+#else
+#define IRQ_MMCI1A	IRQ_SIC_MMCI1A
+#endif
+
+static struct mmc_platform_data mmc1_plat_data = {
+	.ocr_mask	= MMC_VDD_32_33|MMC_VDD_33_34,
+	.status		= mmc_status,
+};
+
+#define UART3_IRQ	{ IRQ_SIC_UART3, NO_IRQ }
+#define UART3_DMA	{ 0x86, 0x87 }
+#define SCI1_IRQ	{ IRQ_SIC_SCI3, NO_IRQ }
+#define SCI1_DMA	{ 0x88, 0x89 }
+#define MMCI1_IRQ	{ IRQ_MMCI1A, IRQ_SIC_MMCI1B }
+#define MMCI1_DMA	{ 0x85, 0 }
+
+/*
+ * These devices are connected via the core APB bridge
+ */
+#define GPIO2_IRQ	{ IRQ_GPIOINT2, NO_IRQ }
+#define GPIO2_DMA	{ 0, 0 }
+#define GPIO3_IRQ	{ IRQ_GPIOINT3, NO_IRQ }
+#define GPIO3_DMA	{ 0, 0 }
+
+/*
+ * These devices are connected via the DMA APB bridge
+ */
+
+/* FPGA Primecells */
+AMBA_DEVICE(uart3, "fpga:09", UART3,    NULL);
+AMBA_DEVICE(sci1,  "fpga:0a", SCI1,     NULL);
+AMBA_DEVICE(mmc1,  "fpga:0b", MMCI1,    &mmc1_plat_data);
+
+/* DevChip Primecells */
+AMBA_DEVICE(gpio2, "dev:e6",  GPIO2,    NULL);
+AMBA_DEVICE(gpio3, "dev:e7",  GPIO3,    NULL);
+
+static struct amba_device *amba_devs[] __initdata = {
+	&uart3_device,
+	&gpio2_device,
+	&gpio3_device,
+	&sci1_device,
+	&mmc1_device,
+};
+
+static int __init versatile_pb_init(void)
+{
+	int i;
+
+	if (machine_is_versatile_pb()) {
+		for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
+			struct amba_device *d = amba_devs[i];
+			amba_device_register(d, &iomem_resource);
+		}
+	}
+
+	return 0;
+}
+
+arch_initcall(versatile_pb_init);
+
+MACHINE_START(VERSATILE_PB, "ARM-Versatile PB")
+	MAINTAINER("ARM Ltd/Deep Blue Solutions Ltd")
+	BOOT_MEM(0x00000000, 0x101f1000, 0xf11f1000)
+	BOOT_PARAMS(0x00000100)
+	MAPIO(versatile_map_io)
+	INITIRQ(versatile_init_irq)
+	.timer		= &versatile_timer,
+	INIT_MACHINE(versatile_init)
+MACHINE_END

arch/arm/mm/Kconfig

@@ -14,6 +14,7 @@ config CPU_ARM610
 	depends on ARCH_RPC
 	select CPU_32v3
 	select CPU_CACHE_V3
+	select CPU_CACHE_VIVT
 	select CPU_COPY_V3
 	select CPU_TLB_V3
 	help
@@ -29,6 +30,7 @@ config CPU_ARM710
 	default y if ARCH_CLPS7500
 	select CPU_32v3
 	select CPU_CACHE_V3
+	select CPU_CACHE_VIVT
 	select CPU_COPY_V3
 	select CPU_TLB_V3
 	help
@@ -47,6 +49,7 @@ config CPU_ARM720T
 	select CPU_32v4
 	select CPU_ABRT_LV4T
 	select CPU_CACHE_V4
+	select CPU_CACHE_VIVT
 	select CPU_COPY_V4WT
 	select CPU_TLB_V4WT
 	help
@@ -64,6 +67,7 @@ config CPU_ARM920T
 	select CPU_32v4
 	select CPU_ABRT_EV4T
 	select CPU_CACHE_V4WT
+	select CPU_CACHE_VIVT
 	select CPU_COPY_V4WB
 	select CPU_TLB_V4WBI
 	help
@@ -84,6 +88,7 @@ config CPU_ARM922T
 	select CPU_32v4
 	select CPU_ABRT_EV4T
 	select CPU_CACHE_V4WT
+	select CPU_CACHE_VIVT
 	select CPU_COPY_V4WB
 	select CPU_TLB_V4WBI
 	help
@@ -102,6 +107,7 @@ config CPU_ARM925T
 	select CPU_32v4
 	select CPU_ABRT_EV4T
 	select CPU_CACHE_V4WT
+	select CPU_CACHE_VIVT
 	select CPU_COPY_V4WB
 	select CPU_TLB_V4WBI
  	help
@@ -115,10 +121,11 @@ config CPU_ARM925T
 # ARM926T
 config CPU_ARM926T
 	bool "Support ARM926T processor" if ARCH_INTEGRATOR
-	depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || ARCH_OMAP730 || ARCH_OMAP1610 || ARCH_OMAP5912
-	default y if ARCH_VERSATILE_PB
+	depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || ARCH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP1610 || ARCH_OMAP5912
+	default y if ARCH_VERSATILE_PB || ARCH_VERSATILE_AB
 	select CPU_32v5
 	select CPU_ABRT_EV5TJ
+	select CPU_CACHE_VIVT
 	select CPU_COPY_V4WB
 	select CPU_TLB_V4WBI
 	help
@@ -136,6 +143,7 @@ config CPU_ARM1020
 	select CPU_32v5
 	select CPU_ABRT_EV4T
 	select CPU_CACHE_V4WT
+	select CPU_CACHE_VIVT
 	select CPU_COPY_V4WB
 	select CPU_TLB_V4WBI
 	help
@@ -152,6 +160,7 @@ config CPU_ARM1020E
 	select CPU_32v5
 	select CPU_ABRT_EV4T
 	select CPU_CACHE_V4WT
+	select CPU_CACHE_VIVT
 	select CPU_COPY_V4WB
 	select CPU_TLB_V4WBI
 	depends on n
@@ -162,6 +171,7 @@ config CPU_ARM1022
 	depends on ARCH_INTEGRATOR
 	select CPU_32v5
 	select CPU_ABRT_EV4T
+	select CPU_CACHE_VIVT
 	select CPU_COPY_V4WB # can probably do better
 	select CPU_TLB_V4WBI
 	help
@@ -178,6 +188,7 @@ config CPU_ARM1026
 	depends on ARCH_INTEGRATOR
 	select CPU_32v5
 	select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
+	select CPU_CACHE_VIVT
 	select CPU_COPY_V4WB # can probably do better
 	select CPU_TLB_V4WBI
 	help
@@ -195,6 +206,7 @@ config CPU_SA110
 	select CPU_32v4 if !ARCH_RPC
 	select CPU_ABRT_EV4
 	select CPU_CACHE_V4WB
+	select CPU_CACHE_VIVT
 	select CPU_COPY_V4WB
 	select CPU_TLB_V4WB
 	help
@@ -214,6 +226,7 @@ config CPU_SA1100
 	select CPU_32v4
 	select CPU_ABRT_EV4
 	select CPU_CACHE_V4WB
+	select CPU_CACHE_VIVT
 	select CPU_TLB_V4WB
 	select CPU_MINICACHE
 
@@ -224,6 +237,7 @@ config CPU_XSCALE
 	default y
 	select CPU_32v5
 	select CPU_ABRT_EV5T
+	select CPU_CACHE_VIVT
 	select CPU_TLB_V4WBI
 	select CPU_MINICACHE
 
@@ -234,6 +248,7 @@ config CPU_V6
 	select CPU_32v6
 	select CPU_ABRT_EV6
 	select CPU_CACHE_V6
+	select CPU_CACHE_VIPT
 	select CPU_COPY_V6
 	select CPU_TLB_V6
 
@@ -286,6 +301,12 @@ config CPU_CACHE_V4WB
 config CPU_CACHE_V6
 	bool
 
+config CPU_CACHE_VIVT
+	bool
+
+config CPU_CACHE_VIPT
+	bool
+
 # The copy-page model
 config CPU_COPY_V3
 	bool

arch/arm/vfp/vfp.h

@@ -249,6 +249,12 @@ struct vfp_double {
 	u64	significand;
 };
 
+/*
+ * VFP_REG_ZERO is a special register number for vfp_get_double
+ * which returns (double)0.0.  This is useful for the compare with
+ * zero instructions.
+ */
+#define VFP_REG_ZERO	16
 extern u64 vfp_get_double(unsigned int reg);
 extern void vfp_put_double(unsigned int reg, u64 val);
 

arch/arm/vfp/vfpdouble.c

@@ -427,12 +427,12 @@ static u32 vfp_double_fcmpe(int dd, int unused, int dm, u32 fpscr)
 
 static u32 vfp_double_fcmpz(int dd, int unused, int dm, u32 fpscr)
 {
-	return vfp_compare(dd, 0, -1, fpscr);
+	return vfp_compare(dd, 0, VFP_REG_ZERO, fpscr);
 }
 
 static u32 vfp_double_fcmpez(int dd, int unused, int dm, u32 fpscr)
 {
-	return vfp_compare(dd, 1, -1, fpscr);
+	return vfp_compare(dd, 1, VFP_REG_ZERO, fpscr);
 }
 
 static u32 vfp_double_fcvts(int sd, int unused, int dm, u32 fpscr)

arch/arm/vfp/vfphw.S

@@ -199,6 +199,11 @@ vfp_get_double:
 	mov	pc, lr
 	.endr
 
+	@ virtual register 16 for compare with zero
+	mov	r0, #0
+	mov	r1, #0
+	mov	pc, lr
+
 	.globl	vfp_put_double
 vfp_put_double:
 	mov	r0, r0, lsr #1

include/asm-arm/arch-omap/serial.h

@@ -4,6 +4,16 @@
  * BRIEF MODULE DESCRIPTION
  * serial definitions
  *
+ * NOTE: There is an error in the description of the transmit trigger levels of
+ * OMAP5910 TRM from January 2003. The transmit trigger level 56 is not 56 but
+ * 32, the transmit trigger level 60 is not 60 but 56!
+ * Additionally, the description of these trigger levels is a little bit
+ * unclear. The trigger level define the number of EMPTY entries in the FIFO.
+ * Thus, if TRIGGER_8 is used, an interrupt is requested if 8 FIFO entries are
+ * empty (and 56 entries are still filled [the FIFO size is 64]). Or: If
+ * TRIGGER_56 is selected, everytime there are less than 8 characters in the
+ * FIFO, an interrrupt is spawned. In other words: The trigger number is equal
+ * the number of characters which can be written without FIFO overrun.
  */
 
 #ifndef __ASM_ARCH_SERIAL_H
@@ -13,7 +23,14 @@
 #define OMAP_UART2_BASE		(unsigned char *)0xfffb0800
 #define OMAP_UART3_BASE		(unsigned char *)0xfffb9800
 #define OMAP_MAX_NR_PORTS	3
-#define PORT_OMAP		16	/* Temporary */
+
+#define is_omap_port(p)	({int __ret = 0;				\
+			if (p == (char*)IO_ADDRESS(OMAP_UART1_BASE) ||	\
+			    p == (char*)IO_ADDRESS(OMAP_UART2_BASE) ||	\
+			    p == (char*)IO_ADDRESS(OMAP_UART3_BASE))	\
+				__ret = 1;				\
+			__ret;						\
+			})
 
 #ifndef __ASSEMBLY__
 
@@ -25,29 +42,6 @@
 
 #define UART_SYSC		0x15
 
-/* OMAP FCR trigger  redefinitions */
-#define UART_FCR_R_TRIGGER_8	0x00	/* Mask for receive trigger set at 8 */
-#define UART_FCR_R_TRIGGER_16	0x40	/* Mask for receive trigger set at 16 */
-#define UART_FCR_R_TRIGGER_56	0x80	/* Mask for receive trigger set at 56 */
-#define UART_FCR_R_TRIGGER_60	0xC0	/* Mask for receive trigger set at 60 */
-
-/* There is an error in the description of the transmit trigger levels of
-   OMAP5910 TRM from January 2003. The transmit trigger level 56 is not
-   56 but 32, the transmit trigger level 60 is not 60 but 56!
-   Additionally, the descritption of these trigger levels is
-   a little bit unclear. The trigger level define the number of EMPTY
-   entries in the FIFO. Thus, if TRIGGER_8 is used, an interrupt is requested
-   if 8 FIFO entries are empty (and 56 entries are still filled [the FIFO
-   size is 64]). Or: If TRIGGER_56 is selected, everytime there are less than
-   8 characters in the FIFO, an interrrupt is spawned. In other words: The
-   trigger number is equal the number of characters which can be
-   written without FIFO overrun */
-
-#define UART_FCR_T_TRIGGER_8	0x00	/* Mask for transmit trigger set at 8 */
-#define UART_FCR_T_TRIGGER_16	0x10	/* Mask for transmit trigger set at 16 */
-#define UART_FCR_T_TRIGGER_32	0x20	/* Mask for transmit trigger set at 32 */
-#define UART_FCR_T_TRIGGER_56	0x30	/* Mask for transmit trigger set at 56 */
-
 #define STD_SERIAL_PORT_DEFNS
 #define EXTRA_SERIAL_PORT_DEFNS
 #define BASE_BAUD 0

include/asm-arm/arch-pxa/pxa-regs.h

@@ -1518,6 +1518,25 @@
 #define RCSR_WDR	(1 << 1)	/* Watchdog Reset */
 #define RCSR_HWR	(1 << 0)	/* Hardware Reset */
 
+#define PWER_GPIO(Nb)	(1 << Nb)	/* GPIO [0..15] wake-up enable     */
+#define PWER_GPIO0	PWER_GPIO (0)	/* GPIO  [0] wake-up enable        */
+#define PWER_GPIO1	PWER_GPIO (1)	/* GPIO  [1] wake-up enable        */
+#define PWER_GPIO2	PWER_GPIO (2)	/* GPIO  [2] wake-up enable        */
+#define PWER_GPIO3	PWER_GPIO (3)	/* GPIO  [3] wake-up enable        */
+#define PWER_GPIO4	PWER_GPIO (4)	/* GPIO  [4] wake-up enable        */
+#define PWER_GPIO5	PWER_GPIO (5)	/* GPIO  [5] wake-up enable        */
+#define PWER_GPIO6	PWER_GPIO (6)	/* GPIO  [6] wake-up enable        */
+#define PWER_GPIO7	PWER_GPIO (7)	/* GPIO  [7] wake-up enable        */
+#define PWER_GPIO8	PWER_GPIO (8)	/* GPIO  [8] wake-up enable        */
+#define PWER_GPIO9	PWER_GPIO (9)	/* GPIO  [9] wake-up enable        */
+#define PWER_GPIO10	PWER_GPIO (10)	/* GPIO [10] wake-up enable        */
+#define PWER_GPIO11	PWER_GPIO (11)	/* GPIO [11] wake-up enable        */
+#define PWER_GPIO12	PWER_GPIO (12)	/* GPIO [12] wake-up enable        */
+#define PWER_GPIO13	PWER_GPIO (13)	/* GPIO [13] wake-up enable        */
+#define PWER_GPIO14	PWER_GPIO (14)	/* GPIO [14] wake-up enable        */
+#define PWER_GPIO15	PWER_GPIO (15)	/* GPIO [15] wake-up enable        */
+#define PWER_RTC	0x80000000	/* RTC alarm wake-up enable        */
+
 
 /*
  * SSP Serial Port Registers

include/asm-arm/arch-s3c2410/dma.h

@@ -199,8 +199,8 @@ struct s3c2410_dma_chan_s {
 
 	/* channel's hardware position and configuration */
 	void __iomem           *regs;        /* channels registers */
+	void __iomem           *addr_reg;    /* data address register */
 	unsigned int           irq;          /* channel irq */
-	unsigned long          addr_reg;     /* data address register */
 	unsigned long          dcon;         /* default value of DCON */
 
 	/* driver handles */

include/asm-arm/arch-s3c2410/regs-gpio.h

@@ -812,7 +812,7 @@
 #define S3C2410_GSTATUS1_2440	   (0x32440000)
 
 #define S3C2410_GSTATUS2_WTRESET   (1<<2)
-#define S3C2410_GSTATUs2_OFFRESET  (1<<1)
+#define S3C2410_GSTATUS2_OFFRESET  (1<<1)
 #define S3C2410_GSTATUS2_PONRESET  (1<<0)
 
 #endif	/* __ASM_ARCH_REGS_GPIO_H */

include/asm-arm/arch-versatile/hardware.h

 /*
  *  linux/include/asm-arm/arch-versatile/hardware.h
  *
- *  This file contains the hardware definitions of the Versatile PB board.
+ *  This file contains the hardware definitions of the Versatile boards.
  *
  *  Copyright (C) 2003 ARM Limited.
  *

include/asm-arm/arch-versatile/platform.h

@@ -47,7 +47,7 @@
 
 
 /* ------------------------------------------------------------------------
- *  Versatile PB Registers
+ *  Versatile Registers
  * ------------------------------------------------------------------------
  * 
  */
@@ -55,10 +55,16 @@
 #define VERSATILE_SYS_SW_OFFSET               0x04
 #define VERSATILE_SYS_LED_OFFSET              0x08
 #define VERSATILE_SYS_OSC0_OFFSET             0x0C
+
+#if defined(CONFIG_ARCH_VERSATILE_PB)
 #define VERSATILE_SYS_OSC1_OFFSET             0x10
 #define VERSATILE_SYS_OSC2_OFFSET             0x14
 #define VERSATILE_SYS_OSC3_OFFSET             0x18
 #define VERSATILE_SYS_OSC4_OFFSET             0x1C
+#elif defined(CONFIG_ARCH_VERSATILE_AB)
+#define VERSATILE_SYS_OSC1_OFFSET             0x1C
+#endif
+
 #define VERSATILE_SYS_LOCK_OFFSET             0x20
 #define VERSATILE_SYS_100HZ_OFFSET            0x24
 #define VERSATILE_SYS_CFGDATA1_OFFSET         0x28
@@ -90,9 +96,13 @@
 #define VERSATILE_SYS_LED                     (VERSATILE_SYS_BASE + VERSATILE_SYS_LED_OFFSET)
 #define VERSATILE_SYS_OSC0                    (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC0_OFFSET)
 #define VERSATILE_SYS_OSC1                    (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC1_OFFSET)
+
+#if defined(CONFIG_ARCH_VERSATILE_PB)
 #define VERSATILE_SYS_OSC2                    (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC2_OFFSET)
 #define VERSATILE_SYS_OSC3                    (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC3_OFFSET)
 #define VERSATILE_SYS_OSC4                    (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC4_OFFSET)
+#endif
+
 #define VERSATILE_SYS_LOCK                    (VERSATILE_SYS_BASE + VERSATILE_SYS_LOCK_OFFSET)
 #define VERSATILE_SYS_100HZ                   (VERSATILE_SYS_BASE + VERSATILE_SYS_100HZ_OFFSET)
 #define VERSATILE_SYS_CFGDATA1                (VERSATILE_SYS_BASE + VERSATILE_SYS_CFGDATA1_OFFSET)
@@ -132,7 +142,7 @@
 
 
 /* ------------------------------------------------------------------------
- *  Versatile PB control registers
+ *  Versatile control registers
  * ------------------------------------------------------------------------
  */
 
@@ -213,6 +223,7 @@
 #define VERSATILE_SSP_BASE             0x101F4000	/* Synchronous Serial Port */
 
 #define VERSATILE_SSMC_BASE            0x20000000	/* SSMC */
+#define VERSATILE_IB2_BASE             0x24000000	/* IB2 module */
 #define VERSATILE_MBX_BASE             0x40000000	/* MBX */
 #define VERSATILE_PCI_BASE             0x41000000	/* PCI Interface */
 #define VERSATILE_SDRAM67_BASE         0x70000000	/* SDRAM banks 6 and 7 */
@@ -255,7 +266,7 @@
 
 
 /* ------------------------------------------------------------------------
- *  Versatile PB Interrupt Controller - control registers
+ *  Versatile Interrupt Controller - control registers
  * ------------------------------------------------------------------------
  * 
  *  Offsets from interrupt controller base 
@@ -483,6 +494,17 @@
 #define VERSATILE_CSR_BASE             0x10000000
 #define VERSATILE_CSR_SIZE             0x10000000
 
+#ifdef CONFIG_ARCH_VERSATILE_AB
+/*
+ * IB2 Versatile/AB expansion board definitions
+ */
+#define VERSATILE_IB2_CAMERA_BANK	0x24000000
+#define VERSATILE_IB2_KBD_DATAREG	0x25000000
+#define VERSATILE_IB2_IER		0x26000000	/* for VICINTSOURCE27 */
+#define VERSATILE_IB2_CTRL		0x27000000
+#define VERSATILE_IB2_STAT		0x27000004
+#endif
+
 #endif
 
 /* 	END */

include/asm-arm/arch-versatile/timex.h

 /*
  *  linux/include/asm-arm/arch-versatile/timex.h
  *
- *  Versatile PB architecture timex specifications
+ *  Versatile architecture timex specifications
  *
  *  Copyright (C) 2003 ARM Limited
  *

include/asm-arm/cacheflush.h

@@ -325,4 +325,63 @@ extern void flush_dcache_page(struct page *);
  */
 #define flush_icache_page(vma,page)	do { } while (0)
 
+#define __cacheid_present(val)		(val != read_cpuid(CPUID_ID))
+#define __cacheid_vivt(val)		((val & (15 << 25)) != (14 << 25))
+#define __cacheid_vipt(val)		((val & (15 << 25)) == (14 << 25))
+#define __cacheid_vipt_nonaliasing(val)	((val & (15 << 25 | 1 << 23)) == (14 << 25))
+#define __cacheid_vipt_aliasing(val)	((val & (15 << 25 | 1 << 23)) == (14 << 25 | 1 << 23))
+
+#if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)
+
+#define cache_is_vivt()			1
+#define cache_is_vipt()			0
+#define cache_is_vipt_nonaliasing()	0
+#define cache_is_vipt_aliasing()	0
+
+#elif defined(CONFIG_CPU_CACHE_VIPT)
+
+#define cache_is_vivt()			0
+#define cache_is_vipt()			1
+#define cache_is_vipt_nonaliasing()					\
+	({								\
+		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\
+		__cacheid_vipt_nonaliasing(__val);			\
+	})
+
+#define cache_is_vipt_aliasing()					\
+	({								\
+		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\
+		__cacheid_vipt_aliasing(__val);				\
+	})
+
+#else
+
+#define cache_is_vivt()							\
+	({								\
+		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\
+		(!__cacheid_present(__val)) || __cacheid_vivt(__val);	\
+	})
+		
+#define cache_is_vipt()							\
+	({								\
+		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\
+		__cacheid_present(__val) && __cacheid_vipt(__val);	\
+	})
+
+#define cache_is_vipt_nonaliasing()					\
+	({								\
+		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\
+		__cacheid_present(__val) &&				\
+		 __cacheid_vipt_nonaliasing(__val);			\
+	})
+
+#define cache_is_vipt_aliasing()					\
+	({								\
+		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\
+		__cacheid_present(__val) &&				\
+		 __cacheid_vipt_aliasing(__val);			\
+	})
+
+#endif
+
 #endif

include/asm-arm/hardware/amba_clcd.h

@@ -22,7 +22,7 @@
 #define CLCD_UBAS 		0x00000010
 #define CLCD_LBAS 		0x00000014
 
-#ifndef CONFIG_ARCH_VERSATILE_PB
+#ifndef CONFIG_ARCH_VERSATILE
 #define CLCD_IENB 		0x00000018
 #define CLCD_CNTL 		0x0000001c
 #else

include/asm-arm/hardware/icst307.h

+/*
+ *  linux/include/asm-arm/hardware/icst307.h
+ *
+ *  Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Support functions for calculating clocks/divisors for the ICS307
+ *  clock generators.  See http://www.icst.com/ for more information
+ *  on these devices.
+ *
+ *  This file is similar to the icst525.h file
+ */
+#ifndef ASMARM_HARDWARE_ICST307_H
+#define ASMARM_HARDWARE_ICST307_H
+
+struct icst307_params {
+	unsigned long	ref;
+	unsigned long	vco_max;	/* inclusive */
+	unsigned short	vd_min;		/* inclusive */
+	unsigned short	vd_max;		/* inclusive */
+	unsigned char	rd_min;		/* inclusive */
+	unsigned char	rd_max;		/* inclusive */
+};
+
+struct icst307_vco {
+	unsigned short	v;
+	unsigned char	r;
+	unsigned char	s;
+};
+
+unsigned long icst307_khz(const struct icst307_params *p, struct icst307_vco vco);
+struct icst307_vco icst307_khz_to_vco(const struct icst307_params *p, unsigned long freq);
+struct icst307_vco icst307_ps_to_vco(const struct icst307_params *p, unsigned long period);
+
+#endif

include/asm-arm/system.h

@@ -57,38 +57,6 @@
 		__val;							\
 	})
 
-#define __cacheid_present(val)		(val != read_cpuid(CPUID_ID))
-#define __cacheid_vivt(val)		((val & (15 << 25)) != (14 << 25))
-#define __cacheid_vipt(val)		((val & (15 << 25)) == (14 << 25))
-#define __cacheid_vipt_nonaliasing(val)	((val & (15 << 25 | 1 << 23)) == (14 << 25))
-#define __cacheid_vipt_aliasing(val)	((val & (15 << 25 | 1 << 23)) == (14 << 25 | 1 << 23))
-
-#define cache_is_vivt()							\
-	({								\
-		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\
-		(!__cacheid_present(__val)) || __cacheid_vivt(__val);	\
-	})
-		
-#define cache_is_vipt()							\
-	({								\
-		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\
-		__cacheid_present(__val) && __cacheid_vipt(__val);	\
-	})
-
-#define cache_is_vipt_nonaliasing()					\
-	({								\
-		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\
-		__cacheid_present(__val) &&				\
-		 __cacheid_vipt_nonaliasing(__val);			\
-	})
-
-#define cache_is_vipt_aliasing()					\
-	({								\
-		unsigned int __val = read_cpuid(CPUID_CACHETYPE);	\
-		__cacheid_present(__val) &&				\
-		 __cacheid_vipt_aliasing(__val);			\
-	})
-
 /*
  * This is used to ensure the compiler did actually allocate the register we
  * asked it for some inline assembly sequences.  Apparently we can't trust