Commit f7982935 authored by Russell King's avatar Russell King

[ARM] Fix EBSA285 CLOCK_TICK_RATE.

The timex/time code requires CLOCK_TICK_RATE to be constant.  We
assume that the platform picks an appropriate clock source such
that we generate an exact HZ value, and set CLOCK_TICK_RATE to
a value where ACTHZ == HZ.
parent f2216ade
...@@ -181,12 +181,13 @@ set_isa_cmos_time(void) ...@@ -181,12 +181,13 @@ set_isa_cmos_time(void)
} }
static unsigned long timer1_latch;
static unsigned long timer1_gettimeoffset (void) static unsigned long timer1_gettimeoffset (void)
{ {
unsigned long value = LATCH - *CSR_TIMER1_VALUE; unsigned long value = timer1_latch - *CSR_TIMER1_VALUE;
return ((tick_nsec / 1000) * value) / LATCH; return ((tick_nsec / 1000) * value) / timer1_latch;
} }
static irqreturn_t static irqreturn_t
...@@ -260,8 +261,10 @@ void __init time_init(void) ...@@ -260,8 +261,10 @@ void __init time_init(void)
machine_is_personal_server()) { machine_is_personal_server()) {
gettimeoffset = timer1_gettimeoffset; gettimeoffset = timer1_gettimeoffset;
timer1_latch = (mem_fclk_21285 + 8 * HZ) / (16 * HZ);
*CSR_TIMER1_CLR = 0; *CSR_TIMER1_CLR = 0;
*CSR_TIMER1_LOAD = LATCH; *CSR_TIMER1_LOAD = timer1_latch;
*CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_AUTORELOAD | TIMER_CNTL_DIV16; *CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_AUTORELOAD | TIMER_CNTL_DIV16;
timer_irq.handler = timer1_interrupt; timer_irq.handler = timer1_interrupt;
......
...@@ -11,8 +11,8 @@ ...@@ -11,8 +11,8 @@
*/ */
/* /*
* On EBSA285 boards, the clock runs at 50MHz and is * We assume a constant here; this satisfies the maths in linux/timex.h
* divided by a 4-bit prescaler. Other boards use an * and linux/time.h. CLOCK_TICK_RATE is actually system dependent, but
* ISA derived timer, and this is unused. * this must be a constant.
*/ */
#define CLOCK_TICK_RATE (mem_fclk_21285 / 16) #define CLOCK_TICK_RATE (50000000/16)
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment