drm/nouveau/kms/nv50-: unify set/clr masks

This is a simplification that'll be used to improve interlock handling.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drivers/gpu/drm/nouveau/dispnv50/atom.h

@@ -105,16 +105,7 @@ struct nv50_head_atom {
 		u8 depth:4;
 	} or;
 
-	union {
-		struct {
-			bool ilut:1;
-			bool core:1;
-			bool curs:1;
-		};
-		u8 mask;
-	} clr;
-
-	union {
+	union nv50_head_atom_mask {
 		struct {
 			bool ilut:1;
 			bool core:1;
@@ -128,7 +119,7 @@ struct nv50_head_atom {
 			bool or:1;
 		};
 		u16 mask;
-	} set;
+	} set, clr;
 };
 
 static inline struct nv50_head_atom *
@@ -184,16 +175,7 @@ struct nv50_wndw_atom {
 		u16 y;
 	} point;
 
-	union {
-		struct {
-			bool ntfy:1;
-			bool sema:1;
-			bool image:1;
-		};
-		u8 mask;
-	} clr;
-
-	union {
+	union nv50_wndw_atom_mask {
 		struct {
 			bool ntfy:1;
 			bool sema:1;
@@ -202,6 +184,6 @@ struct nv50_wndw_atom {
 			bool point:1;
 		};
 		u8 mask;
-	} set;
+	} set, clr;
 };
 #endif

drivers/gpu/drm/nouveau/dispnv50/disp.c

@@ -62,19 +62,12 @@ struct nv50_outp_atom {
 	struct drm_encoder *encoder;
 	bool flush_disable;
 
-	union {
+	union nv50_outp_atom_mask {
 		struct {
 			bool ctrl:1;
 		};
 		u8 mask;
-	} clr;
-
-	union {
-		struct {
-			bool ctrl:1;
-		};
-		u8 mask;
-	} set;
+	} set, clr;
 };
 
 /******************************************************************************

drivers/gpu/drm/nouveau/dispnv50/head.c

@@ -81,14 +81,15 @@ nv50_head_lut_load(struct drm_property_blob *blob, int mode,
 }
 
 void
-nv50_head_flush_clr(struct nv50_head *head, struct nv50_head_atom *asyh, bool y)
+nv50_head_flush_clr(struct nv50_head *head,
+		    struct nv50_head_atom *asyh, bool flush)
 {
-	if (asyh->clr.ilut && (!asyh->set.ilut || y))
-		head->func->ilut_clr(head);
-	if (asyh->clr.core && (!asyh->set.core || y))
-		head->func->core_clr(head);
-	if (asyh->clr.curs && (!asyh->set.curs || y))
-		head->func->curs_clr(head);
+	union nv50_head_atom_mask clr = {
+		.mask = asyh->clr.mask & ~(flush ? 0 : asyh->set.mask),
+	};
+	if (clr.ilut) head->func->ilut_clr(head);
+	if (clr.core) head->func->core_clr(head);
+	if (clr.curs) head->func->curs_clr(head);
 }
 
 void

drivers/gpu/drm/nouveau/dispnv50/wndw.c

@@ -111,12 +111,12 @@ u32
 nv50_wndw_flush_clr(struct nv50_wndw *wndw, u32 interlock, bool flush,
 		    struct nv50_wndw_atom *asyw)
 {
-	if (asyw->clr.sema && (!asyw->set.sema || flush))
-		wndw->func->sema_clr(wndw);
-	if (asyw->clr.ntfy && (!asyw->set.ntfy || flush))
-		wndw->func->ntfy_clr(wndw);
-	if (asyw->clr.image && (!asyw->set.image || flush))
-		wndw->func->image_clr(wndw);
+	union nv50_wndw_atom_mask clr = {
+		.mask = asyw->clr.mask & ~(flush ? 0 : asyw->set.mask),
+	};
+	if (clr.sema ) wndw->func-> sema_clr(wndw);
+	if (clr.ntfy ) wndw->func-> ntfy_clr(wndw);
+	if (clr.image) wndw->func->image_clr(wndw);
 
 	return flush ? wndw->func->update(wndw, interlock) : 0;
 }