Commit f8e17c17 authored by Guo Ren's avatar Guo Ren

csky: Set regs->usp to kernel sp, when the exception is from kernel

In the past, we didn't care about kernel sp when saving pt_reg. But in some
cases, we still need pt_reg->usp to represent the kernel stack before enter
exception.

For cmpxhg in atomic.S, we need save and restore usp for above.
Signed-off-by: default avatarGuo Ren <guoren@linux.alibaba.com>
parent 7f4a5673
...@@ -16,14 +16,16 @@ ...@@ -16,14 +16,16 @@
#define LSAVE_A4 40 #define LSAVE_A4 40
#define LSAVE_A5 44 #define LSAVE_A5 44
#define usp ss1
.macro USPTOKSP .macro USPTOKSP
mtcr sp, ss1 mtcr sp, usp
mfcr sp, ss0 mfcr sp, ss0
.endm .endm
.macro KSPTOUSP .macro KSPTOUSP
mtcr sp, ss0 mtcr sp, ss0
mfcr sp, ss1 mfcr sp, usp
.endm .endm
.macro SAVE_ALL epc_inc .macro SAVE_ALL epc_inc
...@@ -45,7 +47,13 @@ ...@@ -45,7 +47,13 @@
add lr, r13 add lr, r13
stw lr, (sp, 8) stw lr, (sp, 8)
mov lr, sp
addi lr, 32
addi lr, 32
addi lr, 16
bt 2f
mfcr lr, ss1 mfcr lr, ss1
2:
stw lr, (sp, 16) stw lr, (sp, 16)
stw a0, (sp, 20) stw a0, (sp, 20)
...@@ -79,9 +87,10 @@ ...@@ -79,9 +87,10 @@
ldw a0, (sp, 12) ldw a0, (sp, 12)
mtcr a0, epsr mtcr a0, epsr
btsti a0, 31 btsti a0, 31
bt 1f
ldw a0, (sp, 16) ldw a0, (sp, 16)
mtcr a0, ss1 mtcr a0, ss1
1:
ldw a0, (sp, 24) ldw a0, (sp, 24)
ldw a1, (sp, 28) ldw a1, (sp, 28)
ldw a2, (sp, 32) ldw a2, (sp, 32)
...@@ -102,9 +111,9 @@ ...@@ -102,9 +111,9 @@
addi sp, 32 addi sp, 32
addi sp, 8 addi sp, 8
bt 1f bt 2f
KSPTOUSP KSPTOUSP
1: 2:
rte rte
.endm .endm
......
...@@ -31,7 +31,13 @@ ...@@ -31,7 +31,13 @@
mfcr lr, epsr mfcr lr, epsr
stw lr, (sp, 12) stw lr, (sp, 12)
btsti lr, 31
bf 1f
addi lr, sp, 152
br 2f
1:
mfcr lr, usp mfcr lr, usp
2:
stw lr, (sp, 16) stw lr, (sp, 16)
stw a0, (sp, 20) stw a0, (sp, 20)
...@@ -64,8 +70,10 @@ ...@@ -64,8 +70,10 @@
mtcr a0, epc mtcr a0, epc
ldw a0, (sp, 12) ldw a0, (sp, 12)
mtcr a0, epsr mtcr a0, epsr
btsti a0, 31
ldw a0, (sp, 16) ldw a0, (sp, 16)
mtcr a0, usp mtcr a0, usp
mtcr a0, ss0
#ifdef CONFIG_CPU_HAS_HILO #ifdef CONFIG_CPU_HAS_HILO
ldw a0, (sp, 140) ldw a0, (sp, 140)
...@@ -86,6 +94,9 @@ ...@@ -86,6 +94,9 @@
addi sp, 40 addi sp, 40
ldm r16-r30, (sp) ldm r16-r30, (sp)
addi sp, 72 addi sp, 72
bf 1f
mfcr sp, ss0
1:
rte rte
.endm .endm
......
...@@ -17,10 +17,12 @@ ENTRY(csky_cmpxchg) ...@@ -17,10 +17,12 @@ ENTRY(csky_cmpxchg)
mfcr a3, epc mfcr a3, epc
addi a3, TRAP0_SIZE addi a3, TRAP0_SIZE
subi sp, 8 subi sp, 16
stw a3, (sp, 0) stw a3, (sp, 0)
mfcr a3, epsr mfcr a3, epsr
stw a3, (sp, 4) stw a3, (sp, 4)
mfcr a3, usp
stw a3, (sp, 8)
psrset ee psrset ee
#ifdef CONFIG_CPU_HAS_LDSTEX #ifdef CONFIG_CPU_HAS_LDSTEX
...@@ -47,7 +49,9 @@ ENTRY(csky_cmpxchg) ...@@ -47,7 +49,9 @@ ENTRY(csky_cmpxchg)
mtcr a3, epc mtcr a3, epc
ldw a3, (sp, 4) ldw a3, (sp, 4)
mtcr a3, epsr mtcr a3, epsr
addi sp, 8 ldw a3, (sp, 8)
mtcr a3, usp
addi sp, 16
KSPTOUSP KSPTOUSP
rte rte
END(csky_cmpxchg) END(csky_cmpxchg)
......
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