Commit f913edb4 authored by Dave Jones's avatar Dave Jones Committed by Linus Torvalds

[CPUFREQ] add support for ICH4-M chipset in speedstep driver

Intel ICH4-M soutbridges use exactly the same register interface for SpeedStep
as ICH2-M and ICH3-M southbridges -- which makes adding support for this  
bridge (almost) trivial
parent 68b7d00f
...@@ -29,6 +29,9 @@ ...@@ -29,6 +29,9 @@
#include <asm/msr.h> #include <asm/msr.h>
#ifndef PCI_DEVICE_ID_INTEL_82801DB_12
#define PCI_DEVICE_ID_INTEL_82801DB_12 0x24cc
#endif
/* speedstep_chipset: /* speedstep_chipset:
* It is necessary to know which chipset is used. As accesses to * It is necessary to know which chipset is used. As accesses to
...@@ -40,7 +43,7 @@ static struct pci_dev *speedstep_chipset_dev; ...@@ -40,7 +43,7 @@ static struct pci_dev *speedstep_chipset_dev;
#define SPEEDSTEP_CHIPSET_ICH2M 0x00000002 #define SPEEDSTEP_CHIPSET_ICH2M 0x00000002
#define SPEEDSTEP_CHIPSET_ICH3M 0x00000003 #define SPEEDSTEP_CHIPSET_ICH3M 0x00000003
#define SPEEDSTEP_CHIPSET_ICH4M 0x00000004
/* speedstep_processor /* speedstep_processor
*/ */
...@@ -106,6 +109,7 @@ static int speedstep_get_state (unsigned int *state) ...@@ -106,6 +109,7 @@ static int speedstep_get_state (unsigned int *state)
switch (speedstep_chipset) { switch (speedstep_chipset) {
case SPEEDSTEP_CHIPSET_ICH2M: case SPEEDSTEP_CHIPSET_ICH2M:
case SPEEDSTEP_CHIPSET_ICH3M: case SPEEDSTEP_CHIPSET_ICH3M:
case SPEEDSTEP_CHIPSET_ICH4M:
/* get PMBASE */ /* get PMBASE */
pci_read_config_dword(speedstep_chipset_dev, 0x40, &pmbase); pci_read_config_dword(speedstep_chipset_dev, 0x40, &pmbase);
if (!(pmbase & 0x01)) if (!(pmbase & 0x01))
...@@ -166,6 +170,7 @@ static void speedstep_set_state (unsigned int state, int notify) ...@@ -166,6 +170,7 @@ static void speedstep_set_state (unsigned int state, int notify)
switch (speedstep_chipset) { switch (speedstep_chipset) {
case SPEEDSTEP_CHIPSET_ICH2M: case SPEEDSTEP_CHIPSET_ICH2M:
case SPEEDSTEP_CHIPSET_ICH3M: case SPEEDSTEP_CHIPSET_ICH3M:
case SPEEDSTEP_CHIPSET_ICH4M:
/* get PMBASE */ /* get PMBASE */
pci_read_config_dword(speedstep_chipset_dev, 0x40, &pmbase); pci_read_config_dword(speedstep_chipset_dev, 0x40, &pmbase);
if (!(pmbase & 0x01)) if (!(pmbase & 0x01))
...@@ -245,6 +250,7 @@ static int speedstep_activate (void) ...@@ -245,6 +250,7 @@ static int speedstep_activate (void)
switch (speedstep_chipset) { switch (speedstep_chipset) {
case SPEEDSTEP_CHIPSET_ICH2M: case SPEEDSTEP_CHIPSET_ICH2M:
case SPEEDSTEP_CHIPSET_ICH3M: case SPEEDSTEP_CHIPSET_ICH3M:
case SPEEDSTEP_CHIPSET_ICH4M:
{ {
u16 value = 0; u16 value = 0;
...@@ -276,6 +282,14 @@ static int speedstep_activate (void) ...@@ -276,6 +282,14 @@ static int speedstep_activate (void)
*/ */
static unsigned int speedstep_detect_chipset (void) static unsigned int speedstep_detect_chipset (void)
{ {
speedstep_chipset_dev = pci_find_subsys(PCI_VENDOR_ID_INTEL,
PCI_DEVICE_ID_INTEL_82801DB_12,
PCI_ANY_ID,
PCI_ANY_ID,
NULL);
if (speedstep_chipset_dev)
return SPEEDSTEP_CHIPSET_ICH4M;
speedstep_chipset_dev = pci_find_subsys(PCI_VENDOR_ID_INTEL, speedstep_chipset_dev = pci_find_subsys(PCI_VENDOR_ID_INTEL,
PCI_DEVICE_ID_INTEL_82801CA_12, PCI_DEVICE_ID_INTEL_82801CA_12,
PCI_ANY_ID, PCI_ANY_ID,
......
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