Commit fa353e9f authored by Kukjin Kim's avatar Kukjin Kim

Merge branch 'dev/s5pv310-irq' into next-s5pv310

parents a8928ce7 85140ad5
...@@ -132,6 +132,15 @@ void __init s5pv310_init_irq(void) ...@@ -132,6 +132,15 @@ void __init s5pv310_init_irq(void)
gic_cpu_init(0, S5P_VA_GIC_CPU); gic_cpu_init(0, S5P_VA_GIC_CPU);
for (irq = 0; irq < MAX_COMBINER_NR; irq++) { for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
/*
* From SPI(0) to SPI(39) and SPI(51), SPI(53) are
* connected to the interrupt combiner. These irqs
* should be initialized to support cascade interrupt.
*/
if ((irq >= 40) && !(irq == 51) && !(irq == 53))
continue;
combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq), combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
COMBINER_IRQ(irq, 0)); COMBINER_IRQ(irq, 0));
combiner_cascade_irq(irq, IRQ_SPI(irq)); combiner_cascade_irq(irq, IRQ_SPI(irq));
......
...@@ -25,6 +25,8 @@ ...@@ -25,6 +25,8 @@
#define IRQ_SPI(x) S5P_IRQ(x+32) #define IRQ_SPI(x) S5P_IRQ(x+32)
#define IRQ_MCT1 IRQ_SPI(35)
#define IRQ_EINT0 IRQ_SPI(40) #define IRQ_EINT0 IRQ_SPI(40)
#define IRQ_EINT1 IRQ_SPI(41) #define IRQ_EINT1 IRQ_SPI(41)
#define IRQ_EINT2 IRQ_SPI(42) #define IRQ_EINT2 IRQ_SPI(42)
...@@ -36,9 +38,8 @@ ...@@ -36,9 +38,8 @@
#define IRQ_JPEG IRQ_SPI(48) #define IRQ_JPEG IRQ_SPI(48)
#define IRQ_2D IRQ_SPI(49) #define IRQ_2D IRQ_SPI(49)
#define IRQ_PCIE IRQ_SPI(50) #define IRQ_PCIE IRQ_SPI(50)
#define IRQ_SYSTEM_TIMER IRQ_SPI(51) #define IRQ_MCT0 IRQ_SPI(51)
#define IRQ_MFC IRQ_SPI(52) #define IRQ_MFC IRQ_SPI(52)
#define IRQ_WDT IRQ_SPI(53)
#define IRQ_AUDIO_SS IRQ_SPI(54) #define IRQ_AUDIO_SS IRQ_SPI(54)
#define IRQ_AC97 IRQ_SPI(55) #define IRQ_AC97 IRQ_SPI(55)
#define IRQ_SPDIF IRQ_SPI(56) #define IRQ_SPDIF IRQ_SPI(56)
...@@ -85,6 +86,8 @@ ...@@ -85,6 +86,8 @@
#define IRQ_ONENAND_AUDI COMBINER_IRQ(34, 0) #define IRQ_ONENAND_AUDI COMBINER_IRQ(34, 0)
#define IRQ_MCT_L1 COMBINER_IRQ(35, 3)
#define IRQ_EINT4 COMBINER_IRQ(37, 0) #define IRQ_EINT4 COMBINER_IRQ(37, 0)
#define IRQ_EINT5 COMBINER_IRQ(37, 1) #define IRQ_EINT5 COMBINER_IRQ(37, 1)
#define IRQ_EINT6 COMBINER_IRQ(37, 2) #define IRQ_EINT6 COMBINER_IRQ(37, 2)
...@@ -101,7 +104,11 @@ ...@@ -101,7 +104,11 @@
#define IRQ_EINT16_31 COMBINER_IRQ(39, 0) #define IRQ_EINT16_31 COMBINER_IRQ(39, 0)
#define MAX_COMBINER_NR 40 #define IRQ_MCT_L0 COMBINER_IRQ(51, 0)
#define IRQ_WDT COMBINER_IRQ(53, 0)
#define MAX_COMBINER_NR 54
#define S5P_IRQ_EINT_BASE COMBINER_IRQ(MAX_COMBINER_NR, 0) #define S5P_IRQ_EINT_BASE COMBINER_IRQ(MAX_COMBINER_NR, 0)
......
...@@ -24,6 +24,7 @@ static DEFINE_SPINLOCK(irq_controller_lock); ...@@ -24,6 +24,7 @@ static DEFINE_SPINLOCK(irq_controller_lock);
struct combiner_chip_data { struct combiner_chip_data {
unsigned int irq_offset; unsigned int irq_offset;
unsigned int irq_mask;
void __iomem *base; void __iomem *base;
}; };
...@@ -62,6 +63,7 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) ...@@ -62,6 +63,7 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
spin_lock(&irq_controller_lock); spin_lock(&irq_controller_lock);
status = __raw_readl(chip_data->base + COMBINER_INT_STATUS); status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
spin_unlock(&irq_controller_lock); spin_unlock(&irq_controller_lock);
status &= chip_data->irq_mask;
if (status == 0) if (status == 0)
goto out; goto out;
...@@ -104,10 +106,12 @@ void __init combiner_init(unsigned int combiner_nr, void __iomem *base, ...@@ -104,10 +106,12 @@ void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
combiner_data[combiner_nr].base = base; combiner_data[combiner_nr].base = base;
combiner_data[combiner_nr].irq_offset = irq_start; combiner_data[combiner_nr].irq_offset = irq_start;
combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
/* Disable all interrupts */ /* Disable all interrupts */
__raw_writel(0xffffffff, base + COMBINER_ENABLE_CLEAR); __raw_writel(combiner_data[combiner_nr].irq_mask,
base + COMBINER_ENABLE_CLEAR);
/* Setup the Linux IRQ subsystem */ /* Setup the Linux IRQ subsystem */
......
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