Commit fad25222 authored by John Crispin's avatar John Crispin Committed by Ralf Baechle

MIPS: ralink: fix USB frequency scaling

Commit 418d29c8 ("MIPS: ralink: Unify SoC id handling") was not fully
correct. The logic for the SoC check got inverted. We need to check if it
is not a MT76x8.
Signed-off-by: default avatarJohn Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11992/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent e906a5f6
...@@ -459,7 +459,7 @@ void __init ralink_clk_init(void) ...@@ -459,7 +459,7 @@ void __init ralink_clk_init(void)
ralink_clk_add("10000c00.uartlite", periph_rate); ralink_clk_add("10000c00.uartlite", periph_rate);
ralink_clk_add("10180000.wmac", xtal_rate); ralink_clk_add("10180000.wmac", xtal_rate);
if (IS_ENABLED(CONFIG_USB) && is_mt76x8()) { if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) {
/* /*
* When the CPU goes into sleep mode, the BUS clock will be * When the CPU goes into sleep mode, the BUS clock will be
* too low for USB to function properly. Adjust the busses * too low for USB to function properly. Adjust the busses
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment