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nexedi
linux
Commits
fd245f00
Commit
fd245f00
authored
Jun 30, 2006
by
Adrian Bunk
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typo fixes: disadvantadge -> disadvantage
Signed-off-by:
Adrian Bunk
<
bunk@stusta.de
>
parent
0418726b
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Documentation/arm/IXP4xx
Documentation/arm/IXP4xx
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include/asm-arm/arch-ixp4xx/io.h
include/asm-arm/arch-ixp4xx/io.h
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Documentation/arm/IXP4xx
View file @
fd245f00
...
@@ -85,7 +85,7 @@ IXP4xx provides two methods of accessing PCI memory space:
...
@@ -85,7 +85,7 @@ IXP4xx provides two methods of accessing PCI memory space:
2) If > 64MB of memory space is required, the IXP4xx can be
2) If > 64MB of memory space is required, the IXP4xx can be
configured to use indirect registers to access PCI This allows
configured to use indirect registers to access PCI This allows
for up to 128MB (0x48000000 to 0x4fffffff) of memory on the bus.
for up to 128MB (0x48000000 to 0x4fffffff) of memory on the bus.
The disadvanta
d
ge of this is that every PCI access requires
The disadvantage of this is that every PCI access requires
three local register accesses plus a spinlock, but in some
three local register accesses plus a spinlock, but in some
cases the performance hit is acceptable. In addition, you cannot
cases the performance hit is acceptable. In addition, you cannot
mmap() PCI devices in this case due to the indirect nature
mmap() PCI devices in this case due to the indirect nature
...
...
include/asm-arm/arch-ixp4xx/io.h
View file @
fd245f00
...
@@ -38,7 +38,7 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
...
@@ -38,7 +38,7 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
* 2) If > 64MB of memory space is required, the IXP4xx can be configured
* 2) If > 64MB of memory space is required, the IXP4xx can be configured
* to use indirect registers to access PCI (as we do below for I/O
* to use indirect registers to access PCI (as we do below for I/O
* transactions). This allows for up to 128MB (0x48000000 to 0x4fffffff)
* transactions). This allows for up to 128MB (0x48000000 to 0x4fffffff)
* of memory on the bus. The disadvanta
d
ge of this is that every
* of memory on the bus. The disadvantage of this is that every
* PCI access requires three local register accesses plus a spinlock,
* PCI access requires three local register accesses plus a spinlock,
* but in some cases the performance hit is acceptable. In addition,
* but in some cases the performance hit is acceptable. In addition,
* you cannot mmap() PCI devices in this case.
* you cannot mmap() PCI devices in this case.
...
...
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