Commit fe15e8e1 authored by Don Skidmore's avatar Don Skidmore Committed by Jeff Kirsher

ixgbe: add MAC and PHY support for x540

Adds the new x540.c file and Aquantia 1202 PHY for X540 support.
Signed-off-by: default avatarDon Skidmore <donald.c.skidmore@intel.com>
Tested-by: default avatarStephen Ko <stephen.s.ko@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent a391f1d5
...@@ -34,7 +34,7 @@ obj-$(CONFIG_IXGBE) += ixgbe.o ...@@ -34,7 +34,7 @@ obj-$(CONFIG_IXGBE) += ixgbe.o
ixgbe-objs := ixgbe_main.o ixgbe_common.o ixgbe_ethtool.o \ ixgbe-objs := ixgbe_main.o ixgbe_common.o ixgbe_ethtool.o \
ixgbe_82599.o ixgbe_82598.o ixgbe_phy.o ixgbe_sriov.o \ ixgbe_82599.o ixgbe_82598.o ixgbe_phy.o ixgbe_sriov.o \
ixgbe_mbx.o ixgbe_mbx.o ixgbe_x540.o
ixgbe-$(CONFIG_IXGBE_DCB) += ixgbe_dcb.o ixgbe_dcb_82598.o \ ixgbe-$(CONFIG_IXGBE_DCB) += ixgbe_dcb.o ixgbe_dcb_82598.o \
ixgbe_dcb_82599.o ixgbe_dcb_nl.o ixgbe_dcb_82599.o ixgbe_dcb_nl.o
......
...@@ -481,10 +481,12 @@ struct ixgbe_rsc_cb { ...@@ -481,10 +481,12 @@ struct ixgbe_rsc_cb {
enum ixgbe_boards { enum ixgbe_boards {
board_82598, board_82598,
board_82599, board_82599,
board_X540,
}; };
extern struct ixgbe_info ixgbe_82598_info; extern struct ixgbe_info ixgbe_82598_info;
extern struct ixgbe_info ixgbe_82599_info; extern struct ixgbe_info ixgbe_82599_info;
extern struct ixgbe_info ixgbe_X540_info;
#ifdef CONFIG_IXGBE_DCB #ifdef CONFIG_IXGBE_DCB
extern const struct dcbnl_rtnl_ops dcbnl_ops; extern const struct dcbnl_rtnl_ops dcbnl_ops;
extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg, extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
......
...@@ -181,6 +181,10 @@ static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw) ...@@ -181,6 +181,10 @@ static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
phy->ops.get_firmware_version = phy->ops.get_firmware_version =
&ixgbe_get_phy_firmware_version_tnx; &ixgbe_get_phy_firmware_version_tnx;
break; break;
case ixgbe_phy_aq:
phy->ops.get_firmware_version =
&ixgbe_get_phy_firmware_version_generic;
break;
default: default:
break; break;
} }
...@@ -298,7 +302,8 @@ static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw) ...@@ -298,7 +302,8 @@ static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
/* Detect if there is a copper PHY attached. */ /* Detect if there is a copper PHY attached. */
if (hw->phy.type == ixgbe_phy_cu_unknown || if (hw->phy.type == ixgbe_phy_cu_unknown ||
hw->phy.type == ixgbe_phy_tn) { hw->phy.type == ixgbe_phy_tn ||
hw->phy.type == ixgbe_phy_aq) {
media_type = ixgbe_media_type_copper; media_type = ixgbe_media_type_copper;
goto out; goto out;
} }
...@@ -1890,6 +1895,7 @@ static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw) ...@@ -1890,6 +1895,7 @@ static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
hw->phy.ops.identify(hw); hw->phy.ops.identify(hw);
if (hw->phy.type == ixgbe_phy_tn || if (hw->phy.type == ixgbe_phy_tn ||
hw->phy.type == ixgbe_phy_aq ||
hw->phy.type == ixgbe_phy_cu_unknown) { hw->phy.type == ixgbe_phy_cu_unknown) {
hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD, hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
&ext_ability); &ext_ability);
......
...@@ -214,6 +214,7 @@ static int ixgbe_get_settings(struct net_device *netdev, ...@@ -214,6 +214,7 @@ static int ixgbe_get_settings(struct net_device *netdev,
/* Get PHY type */ /* Get PHY type */
switch (adapter->hw.phy.type) { switch (adapter->hw.phy.type) {
case ixgbe_phy_tn: case ixgbe_phy_tn:
case ixgbe_phy_aq:
case ixgbe_phy_cu_unknown: case ixgbe_phy_cu_unknown:
/* Copper 10G-BASET */ /* Copper 10G-BASET */
ecmd->port = PORT_TP; ecmd->port = PORT_TP;
......
...@@ -59,6 +59,7 @@ static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation."; ...@@ -59,6 +59,7 @@ static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
static const struct ixgbe_info *ixgbe_info_tbl[] = { static const struct ixgbe_info *ixgbe_info_tbl[] = {
[board_82598] = &ixgbe_82598_info, [board_82598] = &ixgbe_82598_info,
[board_82599] = &ixgbe_82599_info, [board_82599] = &ixgbe_82599_info,
[board_X540] = &ixgbe_X540_info,
}; };
/* ixgbe_pci_tbl - PCI Device ID Table /* ixgbe_pci_tbl - PCI Device ID Table
......
...@@ -115,6 +115,9 @@ static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) ...@@ -115,6 +115,9 @@ static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
case TN1010_PHY_ID: case TN1010_PHY_ID:
phy_type = ixgbe_phy_tn; phy_type = ixgbe_phy_tn;
break; break;
case AQ1202_PHY_ID:
phy_type = ixgbe_phy_aq;
break;
case QT2022_PHY_ID: case QT2022_PHY_ID:
phy_type = ixgbe_phy_qt; phy_type = ixgbe_phy_qt;
break; break;
...@@ -433,8 +436,8 @@ s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, ...@@ -433,8 +436,8 @@ s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
* Determines the link capabilities by reading the AUTOC register. * Determines the link capabilities by reading the AUTOC register.
*/ */
s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
ixgbe_link_speed *speed, ixgbe_link_speed *speed,
bool *autoneg) bool *autoneg)
{ {
s32 status = IXGBE_ERR_LINK_SETUP; s32 status = IXGBE_ERR_LINK_SETUP;
u16 speed_ability; u16 speed_ability;
...@@ -1410,6 +1413,22 @@ s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, ...@@ -1410,6 +1413,22 @@ s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
return status; return status;
} }
/**
* ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
* @hw: pointer to hardware structure
* @firmware_version: pointer to the PHY Firmware Version
**/
s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
u16 *firmware_version)
{
s32 status = 0;
status = hw->phy.ops.read_reg(hw, AQ_FW_REV, MDIO_MMD_VEND1,
firmware_version);
return status;
}
/** /**
* ixgbe_tn_check_overtemp - Checks if an overtemp occured. * ixgbe_tn_check_overtemp - Checks if an overtemp occured.
* @hw: pointer to hardware structure * @hw: pointer to hardware structure
......
...@@ -106,6 +106,8 @@ s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ...@@ -106,6 +106,8 @@ s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
bool *link_up); bool *link_up);
s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
u16 *firmware_version); u16 *firmware_version);
s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
u16 *firmware_version);
s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw); s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);
s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw); s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
......
...@@ -995,8 +995,10 @@ ...@@ -995,8 +995,10 @@
/* PHY IDs*/ /* PHY IDs*/
#define TN1010_PHY_ID 0x00A19410 #define TN1010_PHY_ID 0x00A19410
#define TNX_FW_REV 0xB #define TNX_FW_REV 0xB
#define AQ1202_PHY_ID 0x03A1B440
#define QT2022_PHY_ID 0x0043A400 #define QT2022_PHY_ID 0x0043A400
#define ATH_PHY_ID 0x03429050 #define ATH_PHY_ID 0x03429050
#define AQ_FW_REV 0x20
/* PHY Types */ /* PHY Types */
#define IXGBE_M88E1145_E_PHY_ID 0x01410CD0 #define IXGBE_M88E1145_E_PHY_ID 0x01410CD0
...@@ -1492,6 +1494,7 @@ ...@@ -1492,6 +1494,7 @@
#define IXGBE_EEC_PRES 0x00000100 /* EEPROM Present */ #define IXGBE_EEC_PRES 0x00000100 /* EEPROM Present */
#define IXGBE_EEC_ARD 0x00000200 /* EEPROM Auto Read Done */ #define IXGBE_EEC_ARD 0x00000200 /* EEPROM Auto Read Done */
#define IXGBE_EEC_FLUP 0x00800000 /* Flash update command */ #define IXGBE_EEC_FLUP 0x00800000 /* Flash update command */
#define IXGBE_EEC_SEC1VAL 0x02000000 /* Sector 1 Valid */
#define IXGBE_EEC_FLUDONE 0x04000000 /* Flash update done */ #define IXGBE_EEC_FLUDONE 0x04000000 /* Flash update done */
/* EEPROM Addressing bits based on type (0-small, 1-large) */ /* EEPROM Addressing bits based on type (0-small, 1-large) */
#define IXGBE_EEC_ADDR_SIZE 0x00000400 #define IXGBE_EEC_ADDR_SIZE 0x00000400
...@@ -1506,7 +1509,9 @@ ...@@ -1506,7 +1509,9 @@
#define IXGBE_EEPROM_SUM 0xBABA #define IXGBE_EEPROM_SUM 0xBABA
#define IXGBE_PCIE_ANALOG_PTR 0x03 #define IXGBE_PCIE_ANALOG_PTR 0x03
#define IXGBE_ATLAS0_CONFIG_PTR 0x04 #define IXGBE_ATLAS0_CONFIG_PTR 0x04
#define IXGBE_PHY_PTR 0x04
#define IXGBE_ATLAS1_CONFIG_PTR 0x05 #define IXGBE_ATLAS1_CONFIG_PTR 0x05
#define IXGBE_OPTION_ROM_PTR 0x05
#define IXGBE_PCIE_GENERAL_PTR 0x06 #define IXGBE_PCIE_GENERAL_PTR 0x06
#define IXGBE_PCIE_CONFIG0_PTR 0x07 #define IXGBE_PCIE_CONFIG0_PTR 0x07
#define IXGBE_PCIE_CONFIG1_PTR 0x08 #define IXGBE_PCIE_CONFIG1_PTR 0x08
...@@ -2173,6 +2178,7 @@ struct ixgbe_atr_input_masks { ...@@ -2173,6 +2178,7 @@ struct ixgbe_atr_input_masks {
enum ixgbe_eeprom_type { enum ixgbe_eeprom_type {
ixgbe_eeprom_uninitialized = 0, ixgbe_eeprom_uninitialized = 0,
ixgbe_eeprom_spi, ixgbe_eeprom_spi,
ixgbe_flash,
ixgbe_eeprom_none /* No NVM support */ ixgbe_eeprom_none /* No NVM support */
}; };
...@@ -2180,12 +2186,14 @@ enum ixgbe_mac_type { ...@@ -2180,12 +2186,14 @@ enum ixgbe_mac_type {
ixgbe_mac_unknown = 0, ixgbe_mac_unknown = 0,
ixgbe_mac_82598EB, ixgbe_mac_82598EB,
ixgbe_mac_82599EB, ixgbe_mac_82599EB,
ixgbe_mac_X540,
ixgbe_num_macs ixgbe_num_macs
}; };
enum ixgbe_phy_type { enum ixgbe_phy_type {
ixgbe_phy_unknown = 0, ixgbe_phy_unknown = 0,
ixgbe_phy_tn, ixgbe_phy_tn,
ixgbe_phy_aq,
ixgbe_phy_cu_unknown, ixgbe_phy_cu_unknown,
ixgbe_phy_qt, ixgbe_phy_qt,
ixgbe_phy_xaui, ixgbe_phy_xaui,
...@@ -2584,6 +2592,7 @@ struct ixgbe_hw { ...@@ -2584,6 +2592,7 @@ struct ixgbe_hw {
u16 subsystem_vendor_id; u16 subsystem_vendor_id;
u8 revision_id; u8 revision_id;
bool adapter_stopped; bool adapter_stopped;
bool force_full_reset;
}; };
struct ixgbe_info { struct ixgbe_info {
......
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