Commit fe7c9be8 authored by Mark A. Greer's avatar Mark A. Greer Committed by Linus Torvalds

[PATCH] ppc32-marvell-host-bridge-support-mv64x60 review fixes

Here is an incremental patch [hopefully] with your concerns addressed.
Note that the arch/ppc/boot code is not kernel code and only exists for a
short period of time before execution jumps to the kernel.
Signed-off-by: default avatarMark A. Greer <mgreer@mvista.com>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 8594ca60
/*
* drivers/serial/mpsc/mpsc_defs.h
*
* Register definitions for the Marvell Multi-Protocol Serial Controller (MPSC),
* Serial DMA Controller (SDMA), and Baud Rate Generator (BRG).
*
* Author: Mark A. Greer <mgreer@mvista.com>
*
* 2004 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef _PPC_BOOT_MPSC_DEFS_H__
#define _PPC_BOOT_MPSC_DEFS_H__
#define MPSC_NUM_CTLRS 2
/*
*****************************************************************************
*
* Multi-Protocol Serial Controller Interface Registers
*
*****************************************************************************
*/
/* Main Configuratino Register Offsets */
#define MPSC_MMCRL 0x0000
#define MPSC_MMCRH 0x0004
#define MPSC_MPCR 0x0008
#define MPSC_CHR_1 0x000c
#define MPSC_CHR_2 0x0010
#define MPSC_CHR_3 0x0014
#define MPSC_CHR_4 0x0018
#define MPSC_CHR_5 0x001c
#define MPSC_CHR_6 0x0020
#define MPSC_CHR_7 0x0024
#define MPSC_CHR_8 0x0028
#define MPSC_CHR_9 0x002c
#define MPSC_CHR_10 0x0030
#define MPSC_CHR_11 0x0034
#define MPSC_MPCR_CL_5 0
#define MPSC_MPCR_CL_6 1
#define MPSC_MPCR_CL_7 2
#define MPSC_MPCR_CL_8 3
#define MPSC_MPCR_SBL_1 0
#define MPSC_MPCR_SBL_2 3
#define MPSC_CHR_2_TEV (1<<1)
#define MPSC_CHR_2_TA (1<<7)
#define MPSC_CHR_2_TTCS (1<<9)
#define MPSC_CHR_2_REV (1<<17)
#define MPSC_CHR_2_RA (1<<23)
#define MPSC_CHR_2_CRD (1<<25)
#define MPSC_CHR_2_EH (1<<31)
#define MPSC_CHR_2_PAR_ODD 0
#define MPSC_CHR_2_PAR_SPACE 1
#define MPSC_CHR_2_PAR_EVEN 2
#define MPSC_CHR_2_PAR_MARK 3
/* MPSC Signal Routing */
#define MPSC_MRR 0x0000
#define MPSC_RCRR 0x0004
#define MPSC_TCRR 0x0008
/*
*****************************************************************************
*
* Serial DMA Controller Interface Registers
*
*****************************************************************************
*/
#define SDMA_SDC 0x0000
#define SDMA_SDCM 0x0008
#define SDMA_RX_DESC 0x0800
#define SDMA_RX_BUF_PTR 0x0808
#define SDMA_SCRDP 0x0810
#define SDMA_TX_DESC 0x0c00
#define SDMA_SCTDP 0x0c10
#define SDMA_SFTDP 0x0c14
#define SDMA_DESC_CMDSTAT_PE (1<<0)
#define SDMA_DESC_CMDSTAT_CDL (1<<1)
#define SDMA_DESC_CMDSTAT_FR (1<<3)
#define SDMA_DESC_CMDSTAT_OR (1<<6)
#define SDMA_DESC_CMDSTAT_BR (1<<9)
#define SDMA_DESC_CMDSTAT_MI (1<<10)
#define SDMA_DESC_CMDSTAT_A (1<<11)
#define SDMA_DESC_CMDSTAT_AM (1<<12)
#define SDMA_DESC_CMDSTAT_CT (1<<13)
#define SDMA_DESC_CMDSTAT_C (1<<14)
#define SDMA_DESC_CMDSTAT_ES (1<<15)
#define SDMA_DESC_CMDSTAT_L (1<<16)
#define SDMA_DESC_CMDSTAT_F (1<<17)
#define SDMA_DESC_CMDSTAT_P (1<<18)
#define SDMA_DESC_CMDSTAT_EI (1<<23)
#define SDMA_DESC_CMDSTAT_O (1<<31)
#define SDMA_DESC_DFLT (SDMA_DESC_CMDSTAT_O | \
SDMA_DESC_CMDSTAT_EI)
#define SDMA_SDC_RFT (1<<0)
#define SDMA_SDC_SFM (1<<1)
#define SDMA_SDC_BLMR (1<<6)
#define SDMA_SDC_BLMT (1<<7)
#define SDMA_SDC_POVR (1<<8)
#define SDMA_SDC_RIFB (1<<9)
#define SDMA_SDCM_ERD (1<<7)
#define SDMA_SDCM_AR (1<<15)
#define SDMA_SDCM_STD (1<<16)
#define SDMA_SDCM_TXD (1<<23)
#define SDMA_SDCM_AT (1<<31)
#define SDMA_0_CAUSE_RXBUF (1<<0)
#define SDMA_0_CAUSE_RXERR (1<<1)
#define SDMA_0_CAUSE_TXBUF (1<<2)
#define SDMA_0_CAUSE_TXEND (1<<3)
#define SDMA_1_CAUSE_RXBUF (1<<8)
#define SDMA_1_CAUSE_RXERR (1<<9)
#define SDMA_1_CAUSE_TXBUF (1<<10)
#define SDMA_1_CAUSE_TXEND (1<<11)
#define SDMA_CAUSE_RX_MASK (SDMA_0_CAUSE_RXBUF | SDMA_0_CAUSE_RXERR | \
SDMA_1_CAUSE_RXBUF | SDMA_1_CAUSE_RXERR)
#define SDMA_CAUSE_TX_MASK (SDMA_0_CAUSE_TXBUF | SDMA_0_CAUSE_TXEND | \
SDMA_1_CAUSE_TXBUF | SDMA_1_CAUSE_TXEND)
/* SDMA Interrupt registers */
#define SDMA_INTR_CAUSE 0x0000
#define SDMA_INTR_MASK 0x0080
/*
*****************************************************************************
*
* Baud Rate Generator Interface Registers
*
*****************************************************************************
*/
#define BRG_BCR 0x0000
#define BRG_BTR 0x0004
#endif /*_PPC_BOOT_MPSC_DEFS_H__ */
...@@ -21,7 +21,7 @@ ...@@ -21,7 +21,7 @@
#include <linux/serial_reg.h> #include <linux/serial_reg.h>
#include <asm/serial.h> #include <asm/serial.h>
#include <asm/mv64x60_defs.h> #include <asm/mv64x60_defs.h>
#include "../../../../drivers/serial/mpsc_defs.h" #include <mpsc_defs.h>
extern void udelay(long); extern void udelay(long);
static void stop_dma(int chan); static void stop_dma(int chan);
...@@ -78,19 +78,19 @@ static struct sdma_regs sdma_regs[2]; ...@@ -78,19 +78,19 @@ static struct sdma_regs sdma_regs[2];
static u32 mpsc_base[2] = { MV64x60_MPSC_0_OFFSET, MV64x60_MPSC_1_OFFSET }; static u32 mpsc_base[2] = { MV64x60_MPSC_0_OFFSET, MV64x60_MPSC_1_OFFSET };
struct mv64x60_rx_desc { struct mv64x60_rx_desc {
volatile u16 bufsize; u16 bufsize;
volatile u16 bytecnt; u16 bytecnt;
volatile u32 cmd_stat; u32 cmd_stat;
volatile u32 next_desc_ptr; u32 next_desc_ptr;
volatile u32 buffer; u32 buffer;
}; };
struct mv64x60_tx_desc { struct mv64x60_tx_desc {
volatile u16 bytecnt; u16 bytecnt;
volatile u16 shadow; u16 shadow;
volatile u32 cmd_stat; u32 cmd_stat;
volatile u32 next_desc_ptr; u32 next_desc_ptr;
volatile u32 buffer; u32 buffer;
}; };
#define MAX_RESET_WAIT 10000 #define MAX_RESET_WAIT 10000
...@@ -121,6 +121,24 @@ static char chan_initialized[2] = { 0, 0 }; ...@@ -121,6 +121,24 @@ static char chan_initialized[2] = { 0, 0 };
SDMA_DESC_CMDSTAT_O; \ SDMA_DESC_CMDSTAT_O; \
} }
#ifdef CONFIG_MV64360
static u32 cpu2mem_tab[MV64x60_CPU2MEM_WINDOWS][2] = {
{ MV64x60_CPU2MEM_0_BASE, MV64x60_CPU2MEM_0_SIZE },
{ MV64x60_CPU2MEM_1_BASE, MV64x60_CPU2MEM_1_SIZE },
{ MV64x60_CPU2MEM_2_BASE, MV64x60_CPU2MEM_2_SIZE },
{ MV64x60_CPU2MEM_3_BASE, MV64x60_CPU2MEM_3_SIZE }
};
static u32 com2mem_tab[MV64x60_CPU2MEM_WINDOWS][2] = {
{ MV64360_MPSC2MEM_0_BASE, MV64360_MPSC2MEM_0_SIZE },
{ MV64360_MPSC2MEM_1_BASE, MV64360_MPSC2MEM_1_SIZE },
{ MV64360_MPSC2MEM_2_BASE, MV64360_MPSC2MEM_2_SIZE },
{ MV64360_MPSC2MEM_3_BASE, MV64360_MPSC2MEM_3_SIZE }
};
static u32 dram_selects[MV64x60_CPU2MEM_WINDOWS] = { 0xe, 0xd, 0xb, 0x7 };
#endif
unsigned long unsigned long
serial_init(int chan, void *ignored) serial_init(int chan, void *ignored)
{ {
...@@ -180,19 +198,6 @@ serial_init(int chan, void *ignored) ...@@ -180,19 +198,6 @@ serial_init(int chan, void *ignored)
/* Set up comm unit to memory mapping windows */ /* Set up comm unit to memory mapping windows */
/* Note: Assumes MV64x60_CPU2MEM_WINDOWS == 4 */ /* Note: Assumes MV64x60_CPU2MEM_WINDOWS == 4 */
u32 cpu2mem_tab[MV64x60_CPU2MEM_WINDOWS][2] = {
{ MV64x60_CPU2MEM_0_BASE, MV64x60_CPU2MEM_0_SIZE },
{ MV64x60_CPU2MEM_1_BASE, MV64x60_CPU2MEM_1_SIZE },
{ MV64x60_CPU2MEM_2_BASE, MV64x60_CPU2MEM_2_SIZE },
{ MV64x60_CPU2MEM_3_BASE, MV64x60_CPU2MEM_3_SIZE }
};
u32 com2mem_tab[MV64x60_CPU2MEM_WINDOWS][2] = {
{ MV64360_MPSC2MEM_0_BASE, MV64360_MPSC2MEM_0_SIZE },
{ MV64360_MPSC2MEM_1_BASE, MV64360_MPSC2MEM_1_SIZE },
{ MV64360_MPSC2MEM_2_BASE, MV64360_MPSC2MEM_2_SIZE },
{ MV64360_MPSC2MEM_3_BASE, MV64360_MPSC2MEM_3_SIZE }
};
u32 dram_selects[MV64x60_CPU2MEM_WINDOWS] = { 0xe, 0xd, 0xb, 0x7 };
enables = MV64x60_REG_READ(MV64360_CPU_BAR_ENABLE) & 0xf; enables = MV64x60_REG_READ(MV64360_CPU_BAR_ENABLE) & 0xf;
prot_bits = 0; prot_bits = 0;
......
...@@ -294,21 +294,31 @@ gt64260_pci_error_int_handler(int irq, void *dev_id, struct pt_regs *regs) ...@@ -294,21 +294,31 @@ gt64260_pci_error_int_handler(int irq, void *dev_id, struct pt_regs *regs)
static int __init static int __init
gt64260_register_hdlrs(void) gt64260_register_hdlrs(void)
{ {
int rc;
/* Register CPU interface error interrupt handler */ /* Register CPU interface error interrupt handler */
request_irq(MV64x60_IRQ_CPU_ERR, gt64260_cpu_error_int_handler, if ((rc = request_irq(MV64x60_IRQ_CPU_ERR,
SA_INTERRUPT, CPU_INTR_STR, 0); gt64260_cpu_error_int_handler, SA_INTERRUPT, CPU_INTR_STR, 0)))
printk(KERN_WARNING "Can't register cpu error handler: %d", rc);
mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0); mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0);
mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0x000000fe); mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0x000000fe);
/* Register PCI 0 error interrupt handler */ /* Register PCI 0 error interrupt handler */
request_irq(MV64360_IRQ_PCI0, gt64260_pci_error_int_handler, if ((rc = request_irq(MV64360_IRQ_PCI0, gt64260_pci_error_int_handler,
SA_INTERRUPT, PCI0_INTR_STR, (void *)0); SA_INTERRUPT, PCI0_INTR_STR, (void *)0)))
printk(KERN_WARNING "Can't register pci 0 error handler: %d",
rc);
mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, 0); mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, 0);
mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, 0x003c0c24); mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, 0x003c0c24);
/* Register PCI 1 error interrupt handler */ /* Register PCI 1 error interrupt handler */
request_irq(MV64360_IRQ_PCI1, gt64260_pci_error_int_handler, if ((rc = request_irq(MV64360_IRQ_PCI1, gt64260_pci_error_int_handler,
SA_INTERRUPT, PCI1_INTR_STR, (void *)1); SA_INTERRUPT, PCI1_INTR_STR, (void *)1)))
printk(KERN_WARNING "Can't register pci 1 error handler: %d",
rc);
mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, 0); mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, 0);
mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, 0x003c0c24); mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, 0x003c0c24);
......
...@@ -367,16 +367,20 @@ static int __init ...@@ -367,16 +367,20 @@ static int __init
mv64360_register_hdlrs(void) mv64360_register_hdlrs(void)
{ {
u32 mask; u32 mask;
int rc;
/* Register CPU interface error interrupt handler */ /* Register CPU interface error interrupt handler */
request_irq(MV64x60_IRQ_CPU_ERR, mv64360_cpu_error_int_handler, if ((rc = request_irq(MV64x60_IRQ_CPU_ERR,
SA_INTERRUPT, CPU_INTR_STR, 0); mv64360_cpu_error_int_handler, SA_INTERRUPT, CPU_INTR_STR, 0)))
printk(KERN_WARNING "Can't register cpu error handler: %d", rc);
mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0); mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0);
mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0x000000ff); mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0x000000ff);
/* Register internal SRAM error interrupt handler */ /* Register internal SRAM error interrupt handler */
request_irq(MV64360_IRQ_SRAM_PAR_ERR, mv64360_sram_error_int_handler, if ((rc = request_irq(MV64360_IRQ_SRAM_PAR_ERR,
SA_INTERRUPT, SRAM_INTR_STR, 0); mv64360_sram_error_int_handler,SA_INTERRUPT,SRAM_INTR_STR, 0)))
printk(KERN_WARNING "Can't register SRAM error handler: %d",rc);
/* /*
* Bit 0 reserved on 64360 and erratum FEr PCI-#11 (PCI internal * Bit 0 reserved on 64360 and erratum FEr PCI-#11 (PCI internal
...@@ -390,14 +394,20 @@ mv64360_register_hdlrs(void) ...@@ -390,14 +394,20 @@ mv64360_register_hdlrs(void)
mask |= 0x1; /* enable DPErr on 64460 */ mask |= 0x1; /* enable DPErr on 64460 */
/* Register PCI 0 error interrupt handler */ /* Register PCI 0 error interrupt handler */
request_irq(MV64360_IRQ_PCI0, mv64360_pci_error_int_handler, if ((rc = request_irq(MV64360_IRQ_PCI0, mv64360_pci_error_int_handler,
SA_INTERRUPT, PCI0_INTR_STR, (void *)0); SA_INTERRUPT, PCI0_INTR_STR, (void *)0)))
printk(KERN_WARNING "Can't register pci 0 error handler: %d",
rc);
mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, 0); mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, 0);
mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, mask); mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, mask);
/* Register PCI 1 error interrupt handler */ /* Register PCI 1 error interrupt handler */
request_irq(MV64360_IRQ_PCI1, mv64360_pci_error_int_handler, if ((rc = request_irq(MV64360_IRQ_PCI1, mv64360_pci_error_int_handler,
SA_INTERRUPT, PCI1_INTR_STR, (void *)1); SA_INTERRUPT, PCI1_INTR_STR, (void *)1)))
printk(KERN_WARNING "Can't register pci 1 error handler: %d",
rc);
mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, 0); mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, 0);
mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, mask); mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, mask);
......
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