- 03 Oct, 2012 40 commits
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Ben Skeggs authored
Hopefully fixed the tlb flush timeout issue. Was able to observe this condition occur occasionally, and it appears the binary driver doesn't wait on the old condition either.. Should give 39-bit DMA addressing on the relevant chipsets. Signed-off-by:Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
Something seems to be missing in regards to flushing specific ranges of the TLB. For the moment, flushing the entire thing seems to make it work alright. Should give 39-bit DMA addressing on the relevant chipsets. v2: allocate contig 16KiB for dummy pages, reported by mwk on irc Signed-off-by: -
Ben Skeggs authored
We don't need to pull the page address out of the page tables on nv4x chips that have a real GART. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
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Martin Peres authored
For now, only 2 control modes are available: - NONE: The fan is never touched (default) - MANUAL: The fan is set to the user-defined fan speed (pwm1) This patch introduces a distinction between ptherm internal fan management and external fan management. The latter is bound to respect the fan mode while the first can still select the speed it wants unless the NONE mode is selected. This is important for automatic fan management. Signed-off-by:
Martin Peres <martin.peres@labri.fr> Signed-off-by:
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Martin Peres authored
This was reported by tizbac on IRC. Signed-off-by:
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Martin Peres authored
v2: Martin Peres <martin.peres@labri.fr> - fixed unintentional use of floating point Signed-off-by:
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Martin Peres authored
The previous driver waited for 250ms to accumulate data. This version times a complete fan rotation and extrapolates to RPM. The fan rotational speed should now be read in less than 250ms (worst case) and usually in less 50ms. Signed-off-by:
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Martin Peres authored
It looks scary because of the size, but I tried to keep the differences minimal. Further patches will fix the actual "driver" code and add new features. v2: change filenames, split to submodules v3: add a missing include v4: Ben Skeggs <bskeggs@redhat.com> - fixed set_defaults() to allow min_duty < 30 (thermal table will override this if it's actually necessary) - fixed set_defaults() to not provide pwm_freq so nv4x (which only has pwm_div) can actually work. the boards using pwm_freq will have a thermal table entry to provide us the value. - removed unused files Signed-off-by:
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Martin Peres authored
v2: perf_table now is more in line with the other functions Signed-off-by:
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Martin Peres authored
This commit also adds a static list of all known devices and their possible i2c addresses. v2: use the common table parsing technique as suggested by darktama Signed-off-by:
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Martin Peres authored
As an accident, it should also fix temperature reading on nv4x. v2: introduce nvbios_therm_entry as advised by darktama Signed-off-by:
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Martin Peres authored
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Dmitry Eremin-Solenikov authored
If nouveau_pm_perflvl_get() fails, pm->profiles list will be left uninitialized, which causes oops during nouveau_pm_fini(). Move INIT_LIST_HEAD before call to nouveau_pm_perflvl_get(). Signed-off-by:
Dmitry Eremin-Solenikov <dmitry_eremin@mentor.com> Signed-off-by:
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Ben Skeggs authored
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Ben Skeggs authored
This will make it more obvious which application caused particular messages. Signed-off-by: -
Ben Skeggs authored
May kill the DRM version completely at some point, undecided.. Signed-off-by: -
Ben Skeggs authored
Can be somewhat more informative that way... Signed-off-by: -
Ben Skeggs authored
Seems to be required to "re-arm" the engines after a vm fault. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
Not really sure how to confirm this 100%, but, the numbers match on all the traces I have for NVCx (2 LTS), NVD9 (1LTS) and NVEx (4LTS). Signed-off-by: -
Ben Skeggs authored
Graphics acceleration is still disabled by default due to lingering issues that need to be solved. Signed-off-by: -
Ben Skeggs authored
Triggers PIBUS interrupts due to register not existing anymore, and as a result HUB_SET_CHAN times out. After this commit, our fuc loads and can accelerate at least fbcon, X, glxgears and OA on NVE4. NVE7 not tested as of yet. Signed-off-by: -
Ben Skeggs authored
Currently identical except the available chipset register lists. This will *not* currently work and is disabled by default because of this. May get merged again later, remains to be seen what further changes will be required. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
Came in useful for debugging another issue earlier, so keep it around. Signed-off-by: -
Marcin Slusarz authored
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Marcin Slusarz <marcin.slusarz@gmail.com> Signed-off-by:
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Marcin Slusarz authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
Will probably flesh the documentation of the classes out a bit too at some later point. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
Future code will use the object class rather than chipset checks in order to identify available channel features. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
This value will match something that's easily available from the engine IRQ handlers, and used to lookup the relevant context. Since the changes in how this is done on each generation match when the major PFIFO changes happened, fifo is responsible for calculating the correct value to avoid duplicating the same code among many engine modules. Signed-off-by: -
Ben Skeggs authored
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