1. 14 Oct, 2020 2 commits
    • Alex Deucher's avatar
      drm/amdgpu/swsmu: init the baco mutex in early_init · 02a1bea6
      Alex Deucher authored
      GPU reset might get called during init time, before
      sw_init has been called.
      Reviewed-by: default avatarKevin Wang <kevin1.wang@amd.com>
      Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
      02a1bea6
    • Rodrigo Siqueira's avatar
      drm/amd/display: Fix module load hangs when connected to an eDP · 44264591
      Rodrigo Siqueira authored
      It was recently introduced a change that enables driver to disable
      streams if pixel clock changes. Consequently, the code path executed in
      the disable vbios function expanded to an encoder verification part.
      The encoder loop is nested inside the pipe count loop, and both loops
      share the 'i' variable in control of their flow. This situation may lead
      to an infinite loop because the encoder loop constantly updates the `i`
      variable, making the first loop always positive. As a result, we can see
      a soft hang during the module load (modprobe amdgpu) and a series of
      dmesg log that looks like this:
      
      kernel:[  124.538727] watchdog: BUG: soft lockup - CPU#2 stuck for 22s!
      [modprobe:1000]
      
      RSP: 0018:ffffabbf419bf0e8 EFLAGS: 00000282
      RAX: ffffffffc0809de0 RBX: ffff93b35ccc0000 RCX: ffff93b366c21800
      RDX: 0000000000000000 RSI: 0000000000000141 RDI: ffff93b35ccc0000
      RBP: ffffabbf419bf108 R08: ffffabbf419bf164 R09: 0000000000000001
      R10: 0000000000000003 R11: 0000000000000003 R12: 0000000008677d40
      R13: 0000000000000141 R14: ffff93b35cfc0000 R15: ffff93b35abc0000
      FS:  00007f1400717540(0000) GS:ffff93b37f680000(0000)
           knlGS:0000000000000000
      CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
      CR2: 00005649b66b0968 CR3: 00000003e0fec000 CR4: 0000000000350ee0
      Call Trace:
       amdgpu_device_rreg+0x17/0x20 [amdgpu]
       amdgpu_cgs_read_register+0x14/0x20 [amdgpu]
       dm_read_reg_func+0x3a/0xb0 [amdgpu]
       get_pixel_clk_frequency_100hz+0x30/0x50 [amdgpu]
       dc_commit_state+0x8f1/0xae0 [amdgpu]
       ? drm_calc_timestamping_constants+0x101/0x160 [drm]
       amdgpu_dm_atomic_commit_tail+0x39d/0x21a0 [amdgpu]
       ? dcn21_validate_bandwidth+0xe5/0x290 [amdgpu]
       ? kfree+0xc3/0x390
       ? dcn21_validate_bandwidth+0xe5/0x290 [amdgpu]
      ...
      RSP: 002b:00007fff26009bd8 EFLAGS: 00000246 ORIG_RAX: 0000000000000139
      RAX: ffffffffffffffda RBX: 000055a8025bea50 RCX: 00007f140085c89d
      RDX: 0000000000000000 RSI: 000055a8025b8290 RDI: 000000000000000c
      RBP: 0000000000040000 R08: 0000000000000000 R09: 0000000000000000
      R10: 000000000000000c R11: 0000000000000246 R12: 000055a8025b8290
      R13: 0000000000000000 R14: 000055a8025bead0 R15: 000055a8025bea50
      
      This issue was fixed by introducing a second variable for the internal
      loop.
      
      Fixes: 8353d30e ("drm/amd/display: disable stream if pixel clock changed with link active")
      Reviewed-by: default avatarRoman Li <Roman.Li@amd.com>
      Reviewed-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
      Signed-off-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
      Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
      44264591
  2. 09 Oct, 2020 8 commits
  3. 05 Oct, 2020 5 commits
  4. 01 Oct, 2020 6 commits
  5. 30 Sep, 2020 8 commits
  6. 29 Sep, 2020 11 commits