Pull "ARM64: DT: Hisilicon Hi6220 soc and hikey board updates for 4.7" from Wei Xu

- Reserve memory regions for Hi6220
- Add sp804 timer node for Hi6220
- Add cpu and cluster level's low power state for Hi6220
- Add gpio configuration nodes for Hi6220
- Add pinctrl configuration nodes for Hi6220
- Add spi related nodes for Hi6220
- Add i2c nodes for Hi6220
- Add i2c nodes to work with mezzanine boards
- Add usb nodes for Hi6220
- Add mailobx node for Hi6220
- Add SRAM node and stub clock node for Hi6220
- Add pinctrl nodes for uarts and enable them
- Add LED nodes for hi6220-hikey board
- Add hi655x pmic node for Hi6220
- Add dwmmc nodes for Hi6220
- Add wifi nodes support for Hi6220-Hikey board
- Register thermal sensor for Hi6220
- Register Hi6220's thermal zone for power allocator
- Add L2 cache topology for Hi6220

* tag 'hi6220-dt-for-4.7' of git://github.com/hisilicon/linux-hisi:
  arm64: dts: Add L2 cache topology to Hi6220
  arm64: dts: register Hi6220's thermal zone for power allocator
  arm64: dts: register Hi6220's thermal sensor
  arm64: dts: add wifi nodes support for hi6220-hikey
  arm64: dts: add dwmmc nodes for hi6220
  arm64: dts: hikey: Add hi655x pmic dts node
  arm64: dts: add LED nodes for hi6220-hikey
  arm64: dts: hi6220: add pinctrl for uarts and enable them
  arm64: dts: add Hi6220's stub clock node
  arm64: dts: add mailbox node for Hi6220
  arm64: dts: Add hi6220 usb node
  arm64: dts: hikey: enable i2c0 and i2c1 for working with mezzanine boards
  arm64: dts: add all hi6220 i2c nodes
  arm64: dts: add Hi6220 spi configuration nodes
  arm64: dts: add Hi6220 pinctrl configuration nodes
  arm64: dts: Add Hi6220 gpio configuration nodes
  arm64: dts: enable idle states for Hi6220
  arm64: dts: add sp804 timer node for Hi6220
  arm64: dts: Reserve memory regions for hi6220

Merge tag 'juno-for-v4.7/dt-updates' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/dt64

Pull "ARMv8 Juno DT updates for v4.7" from Sudeep Holla:

Just one update: Support for external expansion bus useful for
additional hardware e.g.LogicTile Express daughterboards (Brian Starkey)

* tag 'juno-for-v4.7/dt-updates' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
  arm64: dts: juno: Add external expansion bus to DT

Merge tag 'tegra-for-4.7-arm64' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt64

Merge "arm64: tegra: Changes for v4.7-rc1" from Thierry Reding

A couple of cleanups and fixes to various device trees, enable power and
volume keys on Jetson TX1, use stdout-path to define the serial port (so
it doesn't have to be specified on the kernel command-line) and add
Google Pixel C (a.k.a. Smaug) support.

* tag 'tegra-for-4.7-arm64' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  arm64: tegra: Enable cros-ec and charger on Smaug
  arm64: tegra: Add pinmux for Smaug board
  arm64: tegra: Add stdout-path for various boards
  arm64: tegra: Remove unused #power-domain-cells property
  arm64: tegra: Add gpio-keys nodes for Smaug
  arm64: tegra: Enable power and volume keys on Jetson TX1
  arm64: tegra: Add support for Google Pixel C
  arm64: tegra: Replace legacy *,wakeup property with wakeup-source
  arm64: tegra: Fix copy/paste typo in several DTS includes
  arm64: tegra: Remove 0, prefix from unit-addresses

Merge tag 'samsung-dt64-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt64

Merge "Samsung Device Tree ARM64 updates and improvements for v4.7" from Krzysztof Kozlowski:

1. Add PL330 DMA controller and Thermal Management Unit to Exynos 7.

* tag 'samsung-dt64-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  arm64: dts: Add nodes for pdma0 and pdma1 for exynos7
  arm64: dts: exynos: Add TMU node for exynos7

This patch adds the L2 cache topology on Hi6220. Hi6220 has two
clusters, every cluster has 512KiB L2 cache (32KiB x 16 ways).
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

With profiling Hi6220's power modeling so get dynamic coefficient and
sustainable power. So pass these parameters from DT.

Now enable power allocator with only one actor for CPU part, so directly
use cluster0's thermal sensor for monitoring temperature.
Reviewed-by: Javi Merino <javi.merino@arm.com>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

Bind thermal sensor driver for Hi6220.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

Add wifi nodes support for hi6220-hikey
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

Add all three dwmmc nodes description for hi6220
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Xinwei Kong <kong.kongxinwei@hisilicon.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

Add the mfd hi655x dts node and regulator support on hi6220 platform.
Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
Signed-off-by: Fei Wang <w.f@huawei.com>
Signed-off-by: Xinwei Kong <kong.kongxinwei@hisilicon.com>
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Reviewed-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

Add LED nodes for hi6220-hikey. There are total 6 LEDs on HiKey.
Four general purposed, one for WiFi activity, and one for Bluetooth
activity.
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

Add pinctrl for uart2 uart3 and uart4. Enable uart1 uart2 and uart3.
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

Enable SRAM node and stub clock node for Hi6220, which uses mailbox
channel 1 for CPU's frequency change.

Furthermore, add the CPU clock phandle in CPU's node and using
operating-points-v2 to register operating points. So can be used by
cpufreq-dt driver.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

This patch add device mailbox node for Hi6220 in DT.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

Add USB nodes for Hi6220
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

In HiKey board dts file, enable i2c0 and i2c1 for working with 96boards' LS
mezzanine.
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

This patch adds all I2C nodes for the Hi6220 SoC. This hi6220 Soc
use this I2C IP of Synopsys Designware for HiKey board.
Signed-off-by: Xinwei Kong <kong.kongxinwei@hisilicon.com>
Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

Add Hi6220 spi configuration nodes. Disable by default in hi6220.dtsi
and enable it in board dts for usage of 96boards LS mezzanine board.
Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com>
Signed-off-by: Guodong Xu <guodong.xu@linaro.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

Add Hi6220 pinctrl configuration nodes
Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

Add Hi6220 gpio configuration nodes
Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com>
Signed-off-by: Kong Xinwei <kong.kongxinwei@hisilicon.com>
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

Add cpu and cluster level's low power state for Hi6220.
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

Add sp804 timer for hi6220, so it can be used as broadcast timer.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

On Hi6220, below memory regions in DDR have specific purpose:

  0x05e0,0000 - 0x05ef,ffff: For MCU firmware using at runtime;
  0x06df,f000 - 0x06df,ffff: For mailbox message data;
  0x0740,f000 - 0x0740,ffff: For MCU firmware's section;
  0x3e00,0000 - 0x3fff,ffff: For OP-TEE.

This patch reserves these memory regions in DT.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

Add nodes for the ChromeOS Embedded Controller and for the gas gauge
connected to the I2C bus that it controls.
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

The Juno development platform has an external expansion bus which can
be used for additional hardware (e.g. LogicTile Express daughterboards).

Add this bus to the Juno base device-tree.
Acked-by: Liviu Dudau <Liviu.Dudau@arm.com>
Signed-off-by: Brian Starkey <brian.starkey@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>

Merge tag 'v4.7-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64

This contains the rk3368-geekbox as new board, mailbox device
nodes for the core rk3368 and some cleanups for gpio-keys,
mmc and tsadc.

* tag 'v4.7-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  Documentation: devicetree: rockchip: Document rk3368-GeekBox
  arm64: dts: rockchip: Add rk3368 GeekBox dts
  arm64: dts: rockchip: Clean up gpio-keys nodes
  dt-bindings: Add vendor prefix for GeekBuying.com
  arm64: dts: rockchip: Add rk3368 mailbox device nodes
  arm64: dts: rockchip: remove broken-cd from emmc and sdio
  arm64: dts: rockchip: fix the incorrect otp-out pin on rk3368
Signed-off-by: Olof Johansson <olof@lixom.net>

Add initial dtsi file to support lg1312 SoC which based on
Cortex-A53. Also add dts file to support lg1312 reference board
which based on lg1312 SoC.
Signed-off-by: Chanho Min <chanho.min@lge.com>
Signed-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'renesas-arm64-cleanup-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt64

Renesas ARM64 Based SoC Cleanup for v4.7

* Use generic pinctrl properties in DT for salvator-x board

* tag 'renesas-arm64-cleanup-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  arm64: dts: salvator-x: use generic pinctrl properties
Signed-off-by: Olof Johansson <olof@lixom.net>

Add support for a few more Amlogic S905/GXBB based boards: Hardkernel ODROID-C2
and Amlogic P200/P201 boards.
We also fix the memory nodes on the Vega S95 DTS.

* tag 'gxbb-dt64' of https://github.com/carlocaione/linux-meson:
  ARM64: dts: amlogic: Add P200/P201 boards
  ARM64: dts: amlogic: add Hardkernel ODROID-C2
  Documentation: devicetree: amlogic: Document P20x and ODROID-C2 boards
  ARM64: dts: amlogic: update serial aliases
  ARM64: dts: amlogic: Clean up Vega S95 /memory nodes
Signed-off-by: Olof Johansson <olof@lixom.net>

This patch adds device tree nodes for pdma0 and pdma1 controllers
found on exynos7 SoCs.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

Add pinmux node for Tegra210 Smaug board.
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

For Tegra boards, the device-tree alias serial0 is used for the console
and so add the stdout-path information so that the console no longer
needs to be passed via the kernel boot parameters.

For tegra132-norrin the alias serial0 is not defined and so add this.

This has been tested on tegra132-norrin and tegra210-p2371-0000.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

Remove the "#power-domain-cells" property which was incorrectly
included by commit e53095857166 ("arm64: tegra: Add Tegra210
support").
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

Add gpio-keys nodes for the volumn controls, lid switch, tablet mode and
power button.
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
[treding@nvidia.com: use symbolic names for input types and codes]
[treding@nvidia.com: use wakeup-source instead of gpio-key,wakeup]
Signed-off-by: Thierry Reding <treding@nvidia.com>

Add a gpio-keys device tree node to represent the Power, Volume Up and
Volume Down keys found on Jetson TX1.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

Add initial device-tree support for Google Pixel C (a.k.a. Smaug) based
upon Tegra210 SoC with 3 GiB of LPDDR4 RAM.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

Though the keyboard and other driver will continue to support the legacy
"gpio-key,wakeup", "nvidia,wakeup-source" boolean property to enable the
wakeup source, "wakeup-source" is the new standard binding.

This patch replaces all the legacy wakeup properties with the unified
"wakeup-source" property in order to avoid any further copy-paste
duplication.

Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: linux-tegra@vger.kernel.org
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

The comment about the 8250 vs. APB DMA-enabled UART devices that was
added for Tegra20 and Tegra30 in commit b6551bb9 ("ARM: tegra: dts:
add aliases and DMA requestor for serial controller") introduced a typo
that has since spread to various other DTS include files. Fix all
occurrences of this typo.
Suggested-by: Ralf Ramsauer <ralf@ramses-pyramidenbau.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>

When Tegra124 support was first merged the unit-addresses of all devices
were listed with a "0," prefix to encode the reg property's second cell.
It turns out that this notation is not correct, and the "," separator is
only used to separate fields in the unit address (such as the device and
function number in PCI devices), not individual cells for addresses with
more than one cell.
Signed-off-by: Thierry Reding <treding@nvidia.com>