- 20 Mar, 2006 40 commits
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David S. Miller authored
We're about to seriously die in these cases so it is important that the messages make it to the console. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Another case where we have to force ourselves into global register level one. Also make sure the arguments passed to sun4v_do_mna() are correct. This area actually needs some more work, for example spill fixup is not necessarily going to do the right thing for this case. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Just like kvmap_dtlb_longpath we have to force the global register level to one in order to mimick the PSTATE_MG --> PSTATE_AG trasition done on SUN4U. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Caller takes the lock already. Also, fixup the poll loop in sunhv_break_ctl(). Just like in console write, we udelay(2) and use a loop limit of 1000000 iterations. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
So that it will show up as /dev/ttyS0. Otherwise things like installers will try to run on whatever serial port gets probed first. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
For drivers/media/*, noticed by Fabbione. Signed-off-by: David S. Miller <davem@davemloft.net>
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Fabio M. Di Nitto authored
Signed-off-by: Fabio M. Di Nitto <fabbione@ubuntu.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
The SUN4V convention with non-shared TSBs is that the context bit of the TAG is clear. So we have to choose an "invalid" bit and initialize new TSBs appropriately. Otherwise a zero TAG looks "valid". Make sure, for the window fixup cases, that we use the right global registers and that we don't potentially trample on the live global registers in etrap/rtrap handling (%g2 and %g6) and that we put the missing virtual address properly in %g5. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
1) Add error return checking for TLB load hypervisor calls. 2) Don't fallthru to dtlb tsb miss handler from itlb tsb miss handler, oops. 3) On window fixups, propagate fault information to fixup handler correctly. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
It must be ready when we take over the trap table. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
This gives more consistent bogomips and delay() semantics, especially on sun4v. It gives weird looking values though... Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
It should be 1, not 0. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
It's 0x9 not 0xb. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
We need to use the real hardware processor ID when targetting interrupts, not the "define to 0" thing the uniprocessor build gives us. Also, fill in the Node-ID and Agent-ID fields properly on sun4u/Safari. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
If the top-level cnode had multi entries in it's "reg" property, we'd fail. The buffer wasn't large enough in such cases. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
The sibling cpu bringup is extremely fragile. We can only perform the most basic calls until we take over the trap table from the firmware/hypervisor on the new cpu. This means no accesses to %g4, %g5, %g6 since those can't be TLB translated without our trap handlers. In order to achieve this: 1) Change sun4v_init_mondo_queues() so that it can operate in several modes. It can allocate the queues, or install them in the current processor, or both. The boot cpu does both in it's call early on. Later, the boot cpu allocates the sibling cpu queue, starts the sibling cpu, then the sibling cpu loads them in. 2) init_cur_cpu_trap() is changed to take the current_thread_info() as an argument instead of reading %g6 directly on the current cpu. 3) Create a trampoline stack for the sibling cpus. We do our basic kernel calls using this stack, which is locked into the kernel image, then go to our proper thread stack after taking over the trap table. 4) While we are in this delicate startup state, we put 0xdeadbeef into %g4/%g5/%g6 in order to catch accidental accesses. 5) On the final prom_set_trap_table*() call, we put &init_thread_union into %g6. This is a hack to make prom_world(0) work. All that wants to do is restore the %asi register using get_thread_current_ds(). Longer term we should just do the OBP calls to set the trap table by hand just like we do for everything else. This would avoid that silly prom_world(0) issue, then we can remove the init_thread_union hack. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
For 32 cpus and a slow console, it just wedges the machine especially with DETECT_SOFTLOCKUP enabled. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
The whole algorithm was wrong. What we need to do is: 1) Walk each PCI bus above this device on the path to the PCI controller nexus, and for each: a) If interrupt-map exists, apply it, record IRQ controller node b) Else, swivel interrupt number using PCI_SLOT(), use PCI bus parent OBP node as controller node c) Walk up to "controller node" until we hit the first PCI bus in this domain, or "controller node" is the PCI controller OBP node 2) If we walked to PCI controller OBP node, we're done. 3) Else, apply PCI controller interrupt-map to interrupt. There is some stuff that needs to be checked out for ebus and isa, but the PCI part is good to go. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
We'll lose events that way. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
We need to set the global register set _AND_ disable PSTATE_IE in %pstate. The original patch sequence was leaving PSTATE_IE enabled when returning to kernel mode, oops. This fixes the random register corruption being seen on SUN4V. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
So we can read the %gl register for debugging. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
So that free_irq() disable's the IRQ correctly. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Call it from register_one_mondo(). Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
They are bogus and haven't been referenced in years. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
The C function is named sun4v_do_mna not sun4v_mna. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
No trap levels above 2 in privileged mode on SUN4V. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
By calling uart_handle_break(). We'll still do the "sun_do_break()" handling if the user gives two breaks in a row. We should probably do this in the other Sparc serial drivers too. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Forgot to multiply by 8 * 1024, oops. Correct the size constant when the virtual-dma arena is 2GB in size, it should bet 256 not 128. Finally, log some info about the TSB at probe time. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Until the uart is openned, port->info is NULL. Also, init the port->irq properly and give a non-zero port->membase so that the uart device reporting is done. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Need to use ASI_QUAD_LDD_PHYS_4V instead. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
For SUN4V, we were clobbering %o5 to do the hypervisor call. This clobbers the saved %pstate value and we end up writing garbage into that register as a result. Oops. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Needs to use physical addressing just like cheetah_plus. Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller authored
Need to translate through the interrupt-map{,-mask] properties. Signed-off-by: David S. Miller <davem@davemloft.net>
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