- 24 Jan, 2018 8 commits
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Ville Syrjälä authored
Apparently SKL/KBL/CFL need some manual help to get the programmed HDMI vswing to stick. Implement the relevant workaround (display w/a #1143). Note that the relevant chicken bits live in a transcoder register even though the bits affect a specific DDI port rather than a specific transcoder. Hence we must pick the correct transcoder register instance based on the port rather than based on the cpu_transcoder. Also note that for completeness I included support for DDI A/E in the code even though we never have HDMI on those ports. v2: CFL needs the w/a as well (Rodrigo and Art) Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Art Runyan <arthur.j.runyan@intel.com> Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180122174131.28046-1-ville.syrjala@linux.intel.comReviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com>
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Ville Syrjälä authored
Replace the ad-hoc plane indexing scheme used by the frontbuffer tracking with enum plane_id. The old video overlay not being part of the plane_id namespace will just be given the high bit. v2: Drop the unintended whitespace change (Chris) Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
When we finally decide the gpu is idle, that is a good time to shrink our kmem_caches. v3: Defer until an rcu grace period after we idle. v4: Think about epoch wraparound and how likely that is. v5: Use I915_EPOCH_INVALID magic. Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180124113608.14909-2-chris@chris-wilson.co.uk
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Chris Wilson authored
By counting the number of times we have woken up, we have a very simple means of defining an epoch, which will come in handy if we want to perform deferred tasks at the end of an epoch (i.e. while we are going to sleep) without imposing on the next activity cycle. v2: No reason to specify precise number of bits here. v3: Take Tvrtko's advice and reserve 0 as an invalid epoch. Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180124113608.14909-1-chris@chris-wilson.co.uk
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Chris Wilson authored
We only use the preempt context to inject an idle point into execlists. We never need to reference its logical state, so tell the GPU never to load it or save it. v2: BIT(2) for save-inhibit. N.B. Daniele mentioned this bit mbz for ICL, and has been moved into the submission process rather than the context image. Suggested-by:
Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by:
Michel Thierry <michel.thierry@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180123210412.17653-1-chris@chris-wilson.co.uk
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Michel Thierry authored
Newer platforms may have subtle offset changes, which will increase the number of defines, so it is probably better to start moving them to its own header file. Also move the macros used while setting the reg state. v2: Rename to intel_lrc_reg.h, to be consistent with i915_reg.h and intel_guc_reg.h (Chris) v3: License notice shenanigans. v4: Documentation/process/coding-style.rst is always right (Chris) v5: Rebase. Signed-off-by:
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Michel Thierry authored
The macros we use to init the reg_state had the following issues reported by checkpatch --strict. Macro argument reuse 'reg_state' - possible side-effects Macro argument reuse 'pos' - possible side-effects Macro argument reuse 'ppgtt' - possible side-effects spaces preferred around that '+' (ctx:VxV) So fix these issues before they are moved to a new header file. Suggested-by:
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Tvrtko Ursulin authored
We need to generate the event config value using the uAPI class and not the driver internal one. Signed-off-by:
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- 23 Jan, 2018 2 commits
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Rodrigo Vivi authored
Current code always select _CNL_AUX_ANAOVRD1_B register regardless the pw in use. CNL_DISP_PW_AUX_B = 9 CNL_DISP_PW_AUX_C = 10 CNL_DISP_PW_AUX_D = 11 And for pick we want B = 0 C = 1 D = 2 Fixes: ddd39e4b ("drm/i915/cnl: apply Display WA #1178 to fix type C dongles") Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:
Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180123215245.24026-1-rodrigo.vivi@intel.com
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Rodrigo Vivi authored
Let's ignore VBT request if the pin is clearly wrong. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104139 Cc: Kai Heng Feng <kai.heng.feng@canonical.com> Signed-off-by:
Radhakrishna Sripada <radhakrishna.sripada@intel.com>
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- 22 Jan, 2018 6 commits
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Chris Wilson authored
Now that we can read the CSB from the HWSP, we may avoid having to perform mmio reads entirely and so forgo the rigmarole of the forcewake dance. v2: Include forcewake hint for GEM_TRACE readback of mmio. If we don't hold fw ourselves, the reads may return garbage. Signed-off-by:
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Chris Wilson authored
On gen9+, after an idle period the HW will disable the entire power well to conserve power (by preventing current leakage). It takes around a 100 microseconds to bring the power well back online afterwards. With the current hysteresis value of 25us (really 25 * 1280ns), we do not have sufficient time to respond to an interrupt and schedule the next execution before the HW powers itself down. (At present, we prevent this by grabbing the forcewake for prolonged periods of time, but that overkill fixed in the next patch.) The minimum we want to set the power gating hysteresis to is the length of time it takes us to service the GPU, which across a broad spectrum of machines is about 250us. (Note this also brings guc latency into the same ballpark as execlists.) v2: Include some notes on where I plucked the numbers from. Testcase: igt/gem_exec_nop/sequential Signed-off-by:
Sagar Arun Kamble <sagar.a.kamble@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180122135541.32222-1-chris@chris-wilson.co.uk
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Tvrtko Ursulin authored
We fail engine initialization if the scratch VMA cannot be created so there is no point in error handle it later. If the initialization ordering gets messed up, we can explode during development just as well. Signed-off-by:
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Tvrtko Ursulin authored
Render engine constructor helpers must only be called from the render engine constructors, but there is no need to burden the production binaries with warnings which can only be triggered during development. Signed-off-by:
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Manasi Navare authored
In case of eDP because the panel has a fixed mode, the link rate and lane count at which it is trained corresponds to the link BW required to support the native resolution of the panel. In case of panles with lower resolutions where fewer lanes are hooked up internally, that number is reflected in the MAX_LANE_COUNT DPCD register of the panel. So it is pointless to fallback to lower link rate/lane count in case of link training failure on eDP connector since the lower link BW will not support the native resolution of the panel and we cannot prune the preferred mode on the eDP connector. In case of Link training failure on the eDP panel, something is wrong in the HW internally and hence driver errors out with a loud and clear DRM_ERROR message. v2: * Fix the DEBUG_ERROR and add {} in else (Ville Syrjala) Cc: Clinton Taylor <clinton.a.taylor@intel.com> Cc: Jim Bride <jim.bride@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Dave Airlie <airlied@redhat.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:Manasi Navare <manasi.d.navare@intel.com> Reviewed-by:
Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1507835618-23051-1-git-send-email-manasi.d.navare@intel.com
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Chris Wilson authored
As we attempt to allocate pages for use in a new WC stash, direct reclaim may run underneath us and fill up the WC stash. We have to be careful then not to overflow the pvec. Fixes: 66df1014 ("drm/i915: Keep a small stash of preallocated WC pages") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103109Signed-off-by:
Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180121173143.17090-1-chris@chris-wilson.co.uk
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- 20 Jan, 2018 1 commit
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Dhinakaran Pandiyan authored
Avoids some typo pitfalls. Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Reviewed-by:
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- 19 Jan, 2018 22 commits
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Chris Wilson authored
If we fail to allocate a new request, make sure we recover the pages that are in the process of being freed by inserting an RCU barrier. v2: Comment before the shrink and barrier in the error path. Signed-off-by:
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Michal Wajdeczko authored
It looks that GuC log functionality is not fully functional yet and causes issues when enabled by auto(-1) modparam on debug builds. For example, but not limited to: [ 30.062893] ====================================================== [ 30.062894] WARNING: possible circular locking dependency detected [ 30.062895] 4.15.0-rc8-CI-CI_DRM_3648+ #1 Tainted: G U [ 30.062896] ------------------------------------------------------ [ 30.062897] debugfs_test/1268 is trying to acquire lock: [ 30.062898] (&dev->struct_mutex){+.+.}, at: [<00000000e4213449>] i915_mutex_lock_interruptible+0x47/0x130 [i915] [ 30.062921] but task is already holding lock: [ 30.062921] (&mm->mmap_sem){++++}, at: [<00000000dd7adc93>] __do_page_fault+0x106/0x560 [ 30.062924] which lock already depends on the new lock. References: 0ed87953 ("drm/i915/guc: Redefine guc_log_level modparam values") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104693 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104694 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104695Signed-off-by:Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jani Saarinen <jani.saarinen@intel.com> Cc: Tomi Sarvela <tomi.p.sarvela@intel.com> Cc: Marta Lofstedt <marta.lofstedt@intel.com> Cc: Michal Winiarski <michal.winiarski@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180119124926.29844-1-michal.wajdeczko@intel.comReviewed-by:
Michal Winiarski <michal.winiarski@intel.com> Signed-off-by:
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Tvrtko Ursulin authored
Gen11 removes the Resource Streamer, which frees up a big chunk of the context image. BSpec indicates 12544 DWORDs (13 pages), plus one page for PPHWSP. Please notice that, when looking at the BSpec context image table, the right filter has to be applied as some rows are excluded for specific GENs. Also, some rows apply per-subslice (for the calculation above, we have supposed I915_MAX_SUBSLICES = 8). v2: Rebase. v3: Use the right size as per the BSpec. v4: - Rebased on top of the default context size (Rodrigo) - Clarify in the commit message where the subslice calculation comes from. v5: s/12538/12544/ (Daniele) BSpec: 18907 Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Ben Widawsky <benjamin.widawsky@intel.com> (older version) Reviewed-by:Oscar Mateo <oscar.mateo@intel.com> Signed-off-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1515711307-28979-2-git-send-email-oscar.mateo@intel.com
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Oscar Mateo authored
Instead of returning whatever size the latest GEN used. This is because context sizes for new GENs can go up or down, but the only safe thing to do for missing cases is to use the largest known one, whatever that is. Suggested-by:
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Tvrtko Ursulin authored
MMIO addresses and register definition for the new interrupt registers in Gen11. v2: Removed spelt out VCS and VECS bit definitions. (Daniel Vetter) v3: Adjust VCS and VECS. (Daniele Ceraolo Spurio) v4: Bikeshedding (Paulo). Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by:
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Anusha Srivatsa authored
Add the PCI ID for the ICL PCH - ICP. v2: rebased. v3: rebased. v4: fix ICP name. v5: fix the ID mask (Fei Li). v6 (from Paulo): bikesheds. Cc: Li, Fei <fei.li@intel.com> Reviewed-by:
Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by:
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Anusha Srivatsa authored
In ICP, there are three TC ports and 3 DDI ports. v2: - Correct Pin mapping. v3: - Update pin mapping into per platform implementation rather than previous approach of port wise mapping. v4: - Update GMBUS_NUM_PINS (Paulo) v5: - rebase. v6: - Update function name, GMBUS_PIN_NUM (Paulo) v7 (from Paulo): - Make it apply. v8 (from Paulo): - Maintain consistent if ladder ordering. Suggested by: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by:
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Anusha Srivatsa authored
ICP has two backlight controllers - similar to previous platforms like BXT -, but we only use one controller for now, so we can just reuse the CNP code. v2: Remove the usage of ICP_SECOND_PPS_BACKLIGHT register.(Jani) Reuse CNP code since it is very similar.(Ville) v3 (from Paulo): Rebase. v4 (from Paulo): adjust commit message (James) and comment (Rodrigo). Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Acked-by:
James Ausmus <james.ausmus@intel.com> Reviewed-by:
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Anusha Srivatsa authored
ICP, like BXT, has has two panel power sequencers. v2: Simplify the code. Remove unwanted register definitions. Make code as close to BXT style as possible. (Ville) Also, remove the use of ICP_SECOND_PPS_BACKLIGHT for now. Moving forward, if we are sure we need to set this register, we can access it. v3: Use INTEL_GEN(dev_priv), make code more readeable. (Ville) v4 (from Paulo): - Coding style fixes. - Add a missing HAS_PCH_CNP -> gen10+ check. - Rebase. v5: Use per platform checks rather than INTEL_GEN(). v4 of this patch breaks on CoffeeLake, since CFL uses CNP and per platform check makes sense in that case. v6 (from Paulo): - v5 was a patch on top of v4, not a new version. Now v6 is correctly a new version of the original patch. Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Reviewed-by: -
Anusha Srivatsa authored
Add register definitions for setting the rawclock. Set the numerator,denominator and divider values. v2: Simplify the commit message. Simplify the math. Add register bits for numerator. (Paulo) v3 (from Paulo): coding style bikesheds. Reviewed-by:
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Anusha Srivatsa authored
Add the enum additions to ICP PCH. v2 (from Paulo): don't set any platforms to it yet since ICP support is incomplete. v3 (from Rodrigo): Fix ICP name. Reviewed-by:
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Rodrigo Vivi authored
Icelake is an Intel
® Processor containing an Intel® Graphics Controller. This is just an initial Icelake definition. PCI IDs, Icelake support and new features coming in following patches. v2: Add .ddb_size and .has_guc (Michal Wajdeczko). v3: Add the ICL_FEATURES macro (Kelvin Gardiner). v4 (from Paulo): Add missing __initconst (Paulo) and say "graphics controller" instead of something that looks like an official marketing name but isn't (Chris). Reviewed-by: -
Rodrigo Vivi authored
Some Cannonlake SKUs will come with a full split between port A and port E. This will be called port F although it is not a 6th port, but only a split. Note this patch alone is not sufficient for port F enabling, it's just the first step. v2: Fix size of dvo_ports found by Ander. v3: Adding missing cases from intel_bios.c for Port_F v4: Adding other missing cases and fix the commit message. v5: Rebase on top of display headers rework. v6 (from Paulo): improve commit message, bikeshed bit definitions. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Acked-by:
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Mika Kahola authored
We may have fused or unused pipes in our system. Let's check that the pipe in question is within limits of accessible pipes. In case, that we are not able to access the pipe, we return early with a warning. v2: Rephrasing of the commit message (Jani) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103206Reported-by:
Thomas Gleixner <tglx@linutronix.de> Tested-by:
Jaswinder Singh Rajput <jaswinder@perfectintelligent.com> Suggested-by:
Jani Nikula <jani.nikula@intel.com> Reviewed-by:
Mika Kahola <mika.kahola@intel.com> Signed-off-by:
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Ville Syrjälä authored
SKL+ "sprites" no longer have 16KB max stride limit that earlier platforms had. Bump up the limit to 32KB. Cc: Ben Widawsky <ben@bwidawsk.net> Cc: Jason Ekstrand <jason@jlekstrand.net> Cc: Daniel Stone <daniels@collabora.com> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Ville Syrjälä authored
Allow sprites to scan out compressed framebuffers. Since different platforms have a different set of planes that support CCS let's add a small helper to determine whether a specific plane supports CCS or not. Currently that information is spread around in many places, and not all the pieces of code even agree with each other. In addition to allowing sprites to scan out compressed fbs, the other fix here is that we stop rejecting them on pipe C on CNL. Cc: Ben Widawsky <ben@bwidawsk.net> Cc: Jason Ekstrand <jason@jlekstrand.net> Cc: Daniel Stone <daniels@collabora.com> Signed-off-by:
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Ville Syrjälä authored
Split the g4x and snb cases into separate functions to match how we deal with all other platforms. Also sort the switch cases to match the format lists we've declared earlier, to ease comparisons. Cc: Ben Widawsky <ben@bwidawsk.net> Cc: Jason Ekstrand <jason@jlekstrand.net> Cc: Daniel Stone <daniels@collabora.com> Signed-off-by:
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Ville Syrjälä authored
Y/Yf were dropped out from the SKL+ sprite modifier list on account of some watermark issues Daniel Stone was having. My subsequent testing seemed to indicate that things work better now, so add the modifiers back in. v2: Update the commit message with a better explanation Cc: Ben Widawsky <ben@bwidawsk.net> Cc: Jason Ekstrand <jason@jlekstrand.net> Cc: Daniel Stone <daniels@collabora.com> Signed-off-by:
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Ville Syrjälä authored
The unreachable() is very much unreachable and the compiler knows that, so there's no point in having it. Cc: Ben Widawsky <ben@bwidawsk.net> Cc: Jason Ekstrand <jason@jlekstrand.net> Cc: Daniel Stone <daniels@collabora.com> Signed-off-by:
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Abdiel Janulgue authored
4K modes testing by using dummy EDID data has never been working properly on boxes with DP++ (dual-mode) adaptors. The reason for this is that those modes got pruned during hdmi mode validation. intel_hdmi_mode_valid returns CLOCK_HIGH because the pixel clock reported by the 4k mode is higher than dual port TMDS clock limit. However 4k injection does work properly on machines that don't have DP++ adapters because the mode is never validated against the DP++ TMDS clock limit. v2: Don't detect the DP++ limits when we're testing using overridden EDIDs. Make sure to check for the override condition after respecting the value of drm_dp_dual_mode_detect (Jani Nikula). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101649 Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:Abdiel Janulgue <abdiel.janulgue@linux.intel.com> Signed-off-by:
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Jani Nikula authored
drm_edid_to_eld() sets ELD connector type since commit 1d1c3665 ("drm/edid: set ELD connector type in drm_edid_to_eld()"). Remove the redundant update. (Commit c945b8c1 ("drm/edid: build ELD in drm_add_edid_modes()") and commit d471ed04 ("drm/drivers: drop redundant drm_edid_to_eld() calls") are also related.) v2: Rebase, update commit message with commit references. Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Acked-by:
Thierry Reding <treding@nvidia.com> Signed-off-by:
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Jani Nikula authored
No more sing-a-ling. Reported-by:
Adam Jackson <ajax@redhat.com> You're-my-ding-a-ling-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by:
David Weinehall <david.weinehall@linux.intel.com> Signed-off-by:
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- 18 Jan, 2018 1 commit
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Jani Nikula authored
Update VBT defs to reflect revision 216. While at it, default the expected child device struct size to sizeof the size rather than a hardcoded value. v2: Fix bit order (David) Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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