1. 21 May, 2009 3 commits
    • Paul Mundt's avatar
      sh: irq: Teach ipr and intc about dynamically allocating irq_descs. · 05ff3004
      Paul Mundt authored
      This hooks in irq_to_desc_alloc_cpu() to the necessary code paths in the
      intc and ipr controller registration paths. As these are the primary call
      paths for all SH CPUs, this alone will make all CPUs sparse IRQ ready.
      
      There is the added benefit now that each CPU contains specific IPR and
      INTC tables, so only the vectors with interrupt sources backing them will
      ever see an irq_desc instantiation. This effectively packs irq_desc
      down to match the CPU, rather than padding NR_IRQS out to cover the valid
      vector range.
      
      Boards with extra sources will still have to fiddle with the nr_irqs
      setting, but they can continue doing so through the machvec as before.
      Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
      05ff3004
    • Paul Mundt's avatar
      sh: irq: Convert from irq_desc[] to irq_to_desc(). · fa1d43ab
      Paul Mundt authored
      This converts a few places that were using the old irq_desc[] array over
      to the shiny new irq_to_desc() helper. Preperatory work for sparse irq
      support.
      Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
      fa1d43ab
    • Paul Mundt's avatar
      sh: irq: Rework the SR.IMASK bitmap handling. · 55620c86
      Paul Mundt authored
      This tidies up how the SR.IMASK bitmap is managed, using the bitmap API
      directly instead. At the same time, tidy up the irq_chip conversion a
      bit.
      Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
      55620c86
  2. 20 May, 2009 1 commit
  3. 15 May, 2009 2 commits
  4. 14 May, 2009 2 commits
  5. 12 May, 2009 15 commits
  6. 11 May, 2009 9 commits
  7. 10 May, 2009 1 commit
    • Paul Mundt's avatar
      sh: Fix up R0 dependence in __arch_swab16/32. · 567bb8fd
      Paul Mundt authored
      There is nothing in these routines that inherently depends on R0 use.
      Given that these routines are inlined, it is rather easy to blow up the
      compiler by exhausting the spill class when performing a 64-bit swab.
      
      This presently manifests itself as the following:
      
      CC      fs/ocfs2/suballoc.o
      fs/ocfs2/suballoc.c: In function 'ocfs2_reserve_suballoc_bits':
      fs/ocfs2/suballoc.c:638: error: unrecognizable insn:
      (insn 2793 1230 1231 103 arch/sh/include/asm/swab.h:33 (set (reg:HI 853)
              (subreg:HI (reg:SI 149 macl) 2)) -1 (expr_list:REG_DEAD (reg:SI 149 macl)
              (nil)))
      fs/ocfs2/suballoc.c:638: internal compiler error: in extract_insn, at recog.c:1991
      
      This patch switches over to using an arbitrarily assigned register instead.
      
      While the same issue does not exist in the SH-5 case, there is likewise no harm
      in having an alternate register used for the byterev/shari pair.
      Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
      567bb8fd
  8. 09 May, 2009 7 commits