- 03 Oct, 2013 7 commits
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Chris Wilson authored
When we switched to always using a timeout in conjunction with wait_seqno, we lost the ability to detect missed interrupts. Since, we have had issues with interrupts on a number of generations, and they are required to be delivered in a timely fashion for a smooth UX, it is important that we do log errors found in the wild and prevent the display stalling for upwards of 1s every time the seqno interrupt is missed. Rather than continue to fix up the timeouts to work around the interface impedence in wait_event_*(), open code the combination of wait_event[_interruptible][_timeout], and use the exposed timer to poll for seqno should we detect a lost interrupt. v2: In order to satisfy the debug requirement of logging missed interrupts with the real world requirments of making machines work even if interrupts are hosed, we revert to polling after detecting a missed interrupt. v3: Throw in a debugfs interface to simulate broken hw not reporting interrupts. v4: s/EGAIN/EAGAIN/ (Imre) Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by:
Imre Deak <imre.deak@intel.com> [danvet: Don't use the struct typedef in new code.] Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Chris Wilson authored
We missed adding a few cleanup steps for recent additions. Reviewer: Ben Widawsky <ben@bwidawsk.net> Signed-off-by:
Rodrigo Vivi <rodrigo.vivi@gmail.com> Reviewed-by:
Ben Widawsky <ben@bwidawsk.net> Signed-off-by:
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Ben Widawsky authored
This patch attempts to clean up the ring/IA scaling programming in the following ways. 1. Fix the comment about the DDR frequency. The math is 266MHz, not 133MHz. Formula was right, docs are wrong. 2. Mask the DCLK register since I don't know how it is defined on future platforms. 3. use mult_frac instead of magic math. This helps for future platform enabling. v2: Actually use the right patch. The v1 was a mix of things, none of which was right. Note that due to rounding, we actually get different values (slightly higher) for the effective ring frequency. v3: Use 1.25 instead of 1.33 as the original code did. (Jesse) CC: Jesse Barnes <jbarnes@virtuousgeek.org> CC: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by:
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Ville Syrjälä authored
If we ever end up doing the retry loop due to bandwidth constraints, we would rewrite pipe_src_{w,n} based on adjusted_mode timings. But by that time the encoder may have already replaced the adjusted_mode with a fixed panel mode, which would then corrupt pipe_src_{w,h}. v2: Use requested_mode and slap on a big comment from Daniel Signed-off-by:Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Paulo Zanoni authored
This workaround is described in the mode set sequence documentation. When enabling planes for the second pipe, we need to wait for 2 vblanks on the first pipe. This should solve "a flash of screen corruption if planes are enabled on second/third pipe during the time that big FIFO mode is exiting". Watermarks are fun :) v2: Save indentation levels Signed-off-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by:
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Ville Syrjälä authored
Refactor the plane enabling/disabling into helper functions and move the calls to happen as the first thing during .crtc_disable, and the last thing during .crtc_enable. Those are the two clear points where we are sure that the pipe is actually running regardless of the encoder type or hardware generation. v2: Made by Paulo: Remove the code touching everything but the Haswell functions. We need this change on Haswell right now since it fixes a FIFO underrun that we get on pipe A while we enable pipe B (see the workaround notes on the Haswell mode set sequence documentation). We can bring back the code to gens 2-7 later, once they're tested. Signed-off-by:
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Jesse Barnes authored
The global integrated clock source bit resides in DPLL B on VLV, but we were treating it as a per-pipe resource. It needs to be set whenever any PLL is active, so pull setting the bit out of vlv_update_pll and into vlv_enable_pll. Also add a vlv_disable_pll to prevent disabling it when pipe B shuts down. I'm guessing on the references here, I expect this to bite any config where multiple displays are active or displays are moved from pipe to pipe. v2: re-add bits in vlv_update_pll to keep from confusing the state checker v3: use enum pipe checks (Daniel) set CRI clock source early (Ville) consistently set CRI clock source everywhere (Ville) v4: drop unnecessary setting of bit in vlv enable pll (Ville) References: https://bugs.freedesktop.org/show_bug.cgi?id=67245 References: https://bugs.freedesktop.org/show_bug.cgi?id=69693Signed-off-by:
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- 01 Oct, 2013 33 commits
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Jani Nikula authored
Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Damien Lespiau authored
Signed-off-by:
Damien Lespiau <damien.lespiau@intel.com> Reviewed-by:
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Paulo Zanoni authored
For some reason, every single time I try to run module_reload something tries to read the connector sysfs files. This happens after we destroy the encoders and before we destroy the connectors, so when the sysfs read triggers the connector detect() function, intel_conector->encoder points to memory that was already freed. The bad backtrace is just: [<ffffffff8163ca9a>] dump_stack+0x54/0x74 [<ffffffffa00c2c8e>] intel_dp_detect+0x1e/0x4b0 [i915] [<ffffffffa001913d>] status_show+0x3d/0x80 [drm] [<ffffffff813d5340>] dev_attr_show+0x20/0x60 [<ffffffff81221f50>] ? sysfs_read_file+0x80/0x1b0 [<ffffffff81221f79>] sysfs_read_file+0xa9/0x1b0 [<ffffffff811aaf1e>] vfs_read+0x9e/0x170 [<ffffffff811aba4c>] SyS_read+0x4c/0xa0 [<ffffffff8164e392>] system_call_fastpath+0x16/0x1b But if you add tons of memory checking debug options to your Kernel you'll also see: - general protection fault: 0000 - BUG kmalloc-4096 (Tainted: G D W ): Poison overwritten - INFO: Allocated in intel_ddi_init+0x65/0x270 [i915] - INFO: Freed in intel_dp_encoder_destroy+0x69/0xb0 [i915] Among a bunch of other error messages. So this commit just destroys the sysfs files before both the encoder and connectors are freed. Signed-off-by: -
Jani Nikula authored
Neither the DP spec nor the compliance test spec state or imply that we should write the DP_TRAINING_PATTERN_SET at every voltage swing and pre-emphasis change. Indeed we probably shouldn't. So don't. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=49402Signed-off-by:
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Jani Nikula authored
Per DP1.2 spec. Signed-off-by:
Todd Previte <tprevite@gmail.com> Signed-off-by:
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Jesse Barnes authored
It indicates a probable BIOS bug, but it appears to be harmless, and there's nothing the user can do about it anyway, so reduce to a debug msg. I've filed a bug with the BIOS folks about it anyway, so hopefully they'll fix whatever GT SB read they were doing when the GT was off. References: https://bugs.freedesktop.org/show_bug.cgi?id=69396Signed-off-by:
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Damien Lespiau authored
The kernel shouldn't accept invalid modes, just say No. Signed-off-by:
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Damien Lespiau authored
Now that the coding of stereo layout has changed from a bit field to an enum, we need remove that check. Signed-off-by:
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Damien Lespiau authored
This allows us to use fewer bits in the mode structure, leaving room for future work while allowing more stereo layouts types than we could have ever dreamt of. I also exposed the previously private DRM_MODE_FLAG_3D_MASK to set in stone that we are using 5 bits for the stereo layout enum, reserving 32 values. Even with that reservation, we gain 3 bits from the previous encoding. The code adding the mandatory stereo modes needeed to be adapted as it was relying or being able to or stereo layouts together. Suggested-by:
Daniel Vetter <daniel@ffwll.ch> Signed-off-by:
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Jesse Barnes authored
We need to use the clock control reg to figure out how many CZ clks are in 30ns and use that as the basis for our RC6 residency calculations. v2: use ULL everywhere for consistency (Chris) factor out bias for clarity (Chris) References: https://bugs.freedesktop.org/show_bug.cgi?id=69692Signed-off-by: -
Jesse Barnes authored
And add some reg defines while we're at it. Since the units of the RC6 residency counter are actually in CZ clocks, we want to just use the high bits or we'll overflow too frequently. Signed-off-by:
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Ville Syrjälä authored
vlv_find_best_dpll() has an open coded DIV_ROUND_CLOSEST(). Replace it with the real thing. Signed-off-by:
Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by:
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Ville Syrjälä authored
Use 'continue' to get rid of one indent level in vlv_find_best_dpll() Signed-off-by:
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Chon Ming Lee authored
CDCLK is used to generate the gmbus clock. This is normally done by BIOS. Program the value if the BIOS-less system doesn't do it. v2: Move this to intel_i2c_reset to allow reprogram the gmbus frequency during resume. (Daniel) v3: Change GMBUS_FREQ to GMBUSFREQ_VLV, and use VLV_DISPLAY_BASE. (Ville). Remove cdclk_ratio[] table, and calculate the cdclk ratio instead. (Ville). Change the shift then mask for reg read, to mask first, then shift. (Ville). Remove the gmbus frequency calculation = cdclk/1.01. Based on BIOS programming, gmbus frequency = cdclk frequency. (Ville) Add get_disp_clk_div, which can use to get cdclk/czclk divide. v4: Fix the mmio_offset base for CZCLK_CDCLK_FREQ_RATIO, gmbus_freq calculation, and duplicate check for gmbus_freq. (Ville) In VLV, the spec is wrong about 4Mhz reference frequency for GMBUS. It should be 1Mhz. Signed-off-by:
Chon Ming Lee <chon.ming.lee@intel.com> [danvet: Add the comment Ville suggested. Also appease checkpatch a bit.] Reviewed-by:
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Jesse Barnes authored
Still digging up the actual VBT info for this, but wanted to get this out there for testing, or in case others are also bugged by this. This can happen if you boot with an external display connected. In that case, the attached eDP backlight modulation frequency may not be programmed, so we need to use something (in this case the value my BIOS normally programs with just the internal display enabled). v2: fix masking and magic value in read_blc_pwm_ctl (Jani) Signed-off-by:
Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by:
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Damien Lespiau authored
Reviewed-by:
Dave Airlie <airlied@gmail.com> Signed-off-by:
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Damien Lespiau authored
Now that we ask to adjust the crtc timings for stereo modes, the correct pipe_src_w and pipe_src_h can be found in crtc_vdisplay and crtc_hdisplay. v2: Add comment about why pipe_src_w/h need to be set afert set_crtcinfo() (Daniel Vetter) Reviewed-by: -
Damien Lespiau authored
When scanning out big stereo buffers that are actually bigger that their natural 2D counterpart, we need to blow up the crtc timings as well. Not that this is only done for frame packing as this is the only stereo mode currently exposed needing this kind of ajdustements. Reviewed-by:
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Damien Lespiau authored
struct drm_mode_display now has a separate crtc_ version of the clock to be used when we're talking about the timings given to the harwadre (was far as the mode is concerned). This commit is really the result of a git grep adjusted_mode.*clock and replacing those by adjusted_mode.crtc_clock. No functional change. v2: Rebased on drm-intel-queued-next Reviewed-by:
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Damien Lespiau authored
We want to dump the parameters given to the hardware, so let's use crtc_clock here. Reviewed-by:
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Damien Lespiau authored
Some stereo modes, like frame packing, need a larger CRTC viewport than the "natural" underlying 2D mode and thus drm_crtc_check_viewport() needs to query the adjusted mode to use the correct h/vdisplay. Reviewed-by:
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Damien Lespiau authored
Both setcrtc and page_flip are checking that the framebuffer is big enough for the defined crtc viewport (x, y, hdisplay, vdisplay). Factor that code out in a single function. Reviewed-by:
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Damien Lespiau authored
When using the frame packing and a single big framebuffer, some hardware requires that we do everything like if we were scanning out the big buffer itself. Let's instrument drm_mode_set_crtcinfo() to be able to do this adjustement if the driver is asking for it. v2: Use crtc_vtotal and multiply the clock by 2 instead of reconstructing it (Ville Syrjälä) Suggested-by: -
Damien Lespiau authored
Just like the various timings, make it possible to have a clock field what we can tweak before giving it to hardware. Reviewed-by:
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Damien Lespiau authored
This field is unused. Garbage collect it. Reviewed-by:
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Damien Lespiau authored
This field was only accessed by the nouveau driver, but never set. So concluded we can rid of this one. Acked-by:
Ben Skeggs <bskeggs@redhat.com> Reviewed-by:
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Damien Lespiau authored
Just like with interlaced or double scan modes, make stereo modes a per-connector opt-in to give a chance to driver authors to make it work before enabling it. Suggested-by:
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Damien Lespiau authored
This allows to expose the alternate clock versions of the stereo modes. Reviewed-by:
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Damien Lespiau authored
When scanning out a stereo mode, the AVI infoframe vic field has to be the underlyng 2D VIC. Before that commit, we weren't matching the CEA mode because of the extra stereo flag and then were setting the VIC field in the AVI infoframe to 0. Reviewed-by:
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Damien Lespiau authored
When scanning out a 3D mode on HDMI, we need to send an HDMI infoframe with the corresponding layout to the sink. v2: Make s3d_structure_from_display_mode() less subtle (Ville Syrjälä) Reviewed-by:
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Damien Lespiau authored
When setting a stereo 3D mode, there can be only one bit set describing the layout of the frambuffer(s). So reject invalid modes early. Reviewed-by:
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Damien Lespiau authored
So we respect a nice design of having similar functions at the same level, in this case: do_hdmi_vsdb_modes() - add_hdmi_mandatory_stereo_modes() - add_hdmi_mode() Reviewed-by:
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Damien Lespiau authored
For now, let's just look at the 3D_present flag of the CEA HDMI vendor block to detect if the sink supports a small list of then mandatory 3D formats. See the HDMI 1.4a 3D extraction for detail: http://www.hdmi.org/manufacturer/specification.aspx v2: Rename freq to vrefresh, make the mandatory structure a bit more compact, fix some white space issues and add a couple of const (Ville Syrjälä) Reviewed-by:
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