- 11 Feb, 2020 26 commits
-
-
Alex Deucher authored
Rather than the FEATURE_ID flags. Avoids a possible reading past the end of the array. Reviewed-by:
Evan Quan <evan.quan@amd.com> Reported-by:
Aleksandr Mezin <mezin.alexander@gmail.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
-
Alex Deucher authored
Update to the latest changes. Reviewed-by:
-
xinhui pan authored
As root PD has no parent, we just need move its status to idle. Suggested-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
xinhui pan <xinhui.pan@amd.com> Reviewed-by:
-
Guchun Chen authored
Former comment looks to be one intended behavior in code, actually it's not. So correct it. Suggested-by:
Guchun Chen <guchun.chen@amd.com> Acked-by:
-
Prike Liang authored
SMU12 not support WORKLOAD_DEFAULT_BIT and WORKLOAD_PPLIB_POWER_SAVING_BIT. Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Reviewed-by:
-
Evan Quan authored
To pair the latest SMU firmwares. Signed-off-by:
Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by:
-
Sung Lee authored
[WHY] Programming DPPCLK to the same value currently set may cause underflow while playing video in certain conditions. [HOW] Only program DPPCLK if clock is not the same as the previous value programmed. Signed-off-by:
Sung Lee <sung.lee@amd.com> Reviewed-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
-
Nicholas Kazlauskas authored
[Why] In the case where we do have these passed in then we should be using these instead of the registers - those are only programmed when booting the adapter as primary. [How] Check if fb_base/fb_offset are non-zero. The value of 0 is invalid for fb_base but is valid for fb_offset on dGPU. Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Reviewed-by:
-
Wyatt Wood authored
[Why] Driver needs to know PSR state. [How] Use GPINT to call to firmware and get psr state. Signed-off-by:
Wyatt Wood <wyatt.wood@amd.com> Reviewed-by:
-
Nicholas Kazlauskas authored
[Why] In DCN hardware sequencer we do actually call ATOM_INIT correctly per pipe. The workaround is not necessary for command table offloading. [How] Drop the workaround since it's not needed. Signed-off-by:
Chris Park <Chris.Park@amd.com> Acked-by:
-
Martin Leung authored
[why] customer issue: found that for their specific panel, EDID register space being overwritten during SCDC read write [how] customer accepted HDMI 2 features not working - disabled SCDC read/write as well as HDMI 2 in general based on monitor patch Signed-off-by:
Martin Leung <martin.leung@amd.com> Reviewed-by:
-
Dmytro Laktyushkin authored
Currently odm scaling calculations are only done when adding initial odm pipe. Any scaling re-calculations will mess up odm because of this. This change resolves the problem by updating scaling split logic to handle odm. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
Michael Strauss <Michael.Strauss@amd.com> Acked-by:
-
Anthony Koo authored
Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Reviewed-by:
-
Nikola Cornij authored
In the struct dc_panel_patch, we have a field named manage_secondary_link which is not used by any part of the code. This commit drops the unused field. Signed-off-by:
Nikola Cornij <nikola.cornij@amd.com> Reviewed-by:
Joshua Aberback <Joshua.Aberback@amd.com> Acked-by:
-
Anthony Koo authored
[Why] Some register defines are redundant or updated [How] Update register defines Remove some redundant defines Signed-off-by:
Sun peng Li <Sunpeng.Li@amd.com> Signed-off-by:
-
Peikang Zhang authored
[Why] in dcn10_apply_ctx_for_surface(), if we hit !top_pipe_to_program, pipe_ctx->update_flags could not get cleared. [How] Moved clearing pipe_ctx->update_flags logic before if (!top_pipe_to_program) to gurantee pipe_ctx->update_flags get cleared. Signed-off-by:
Peikang Zhang <peikang.zhang@amd.com> Reviewed-by:
-
Rodrigo Siqueira authored
Several modern displays support HDR/OLED panel, and one of the interesting changes provided by this technology is the new approach for handling backlight. More precisely, in the traditional way, we use PWM to manage display backlight; however, with HDR/OLED we begin to use DP Aux channel for adjusting the backlight. This patch, enable the backlight control in HDR/OLED display via DP Aux. Signed-off-by:
Harry Wentland <Harry.Wentland@amd.com> Acked-by:
-
Rodrigo Siqueira authored
Introduce vendor-specific registers for handling backlight via AUX. Signed-off-by:
-
Wyatt Wood authored
[Why] Set version is currently not called. [How] Add call to set version from copy settings. This should be the only time this is called as the eDP caps should never change. Signed-off-by:
-
Calvin Hou authored
[WHY] Vendor dongle requires propietary OUI and handshake sequence. [HOW] Add a new structure to dc_init_data, to allow creator to pass an override vendor_oui. This value will be written to DP_SOURCE_OUI instead of AMD signature, when dpcd_set_source_specific_data is called. Signed-off-by:
Calvin Hou <Calvin.Hou@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
-
Wyatt Wood authored
[Why] Taking up unnecessary space. [How] Remove unused values from psr struct. Signed-off-by:
-
Nicholas Kazlauskas authored
[Why] With the fallback case in place for command table offloading via DMCUB it's no longer an error for the command table to be missing specific entries. [How] Drop the BREAK_TO_DEBUGGER(); Signed-off-by:
-
Martin Leung authored
[why] before we exit early in edp_reciever_ready if we detect that panel is not edp or below rev 1.2. This will skip the backlight/t7 delay panel patch. [how] edit logic to ensure panel patch is applied regardless of edp rev. Signed-off-by:
-
James Zhu authored
Fix warning during switching to dpg pause mode for VCN firmware Version ENC: 1.1 DEC: 1 VEP: 0 Revision: 16 Signed-off-by:
James Zhu <James.Zhu@amd.com> Acked-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
-
Guchun Chen authored
GDS clear workaround will cause gfx failure in suspend/resume case. [ 98.679559] [drm:amdgpu_device_ip_late_init [amdgpu]] *ERROR* late_init of IP block <gfx_v9_0> failed -110 [ 98.679561] PM: dpm_run_callback(): pci_pm_resume+0x0/0xa0 returns -110 [ 98.679562] PM: Device 0000:03:00.0 failed to resume async: error -110 As this workaround is specific to the HW bug of GDS's ECC error existing in cold boot up, so bypass this workaround in suspend/ resume case after booting up. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
-
Jack Zhang authored
With the recent patch to unify VRAM address for driver table(a83f82e). VF cannot dump table info any more because SMU_MSG_SetDriverDramAddrHigh/Low were deleted in the function of smu_update_table. Therefore, VF also needs to set driver_table address in smu_hw_init to fix this regression issue. Signed-off-by:
Jack Zhang <Jack.Zhang1@amd.com> Acked-by:
-
- 07 Feb, 2020 9 commits
-
-
Christian König authored
Make use of the better performance here as well. This patch is only compile tested! v2: fix calculation bug pointed out by Felix Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Acked-by:
Jonathan Kim <Jonathan.Kim@amd.com> Signed-off-by:
-
Christian König authored
This speeds up the access quite a bit from 2.2 MB/s to 2.9 MB/s on 32bit and 12,8 MB/s on 64bit. Signed-off-by:
-
Christian König authored
This should speed up debugging VRAM access a lot. v2: add HDP flush/invalidate Signed-off-by:
-
Christian König authored
Only write the _HI register when necessary. Signed-off-by:
-
Jonathan Kim authored
hwc->conf was designated specifically for AMD APU IOMMU purposes. This could cause problems in performance and/or function since APU IOMMU implementation is elsewhere. Also hwc->conf and hwc->config are different members of an anonymous union so hwc->conf aliases as hw->last_tag. Signed-off-by:
-
Daniel Kolesa authored
On PowerPC, the compiler will tag object files with whether they use hard or soft float FP ABI and whether they use 64 or 128-bit long double ABI. On systems with 64-bit long double ABI, a tag will get emitted whenever a double is used, as on those systems a long double is the same as a double. This will prevent linkage as other files are being compiled with hard-float. On ppc64, this code will never actually get used for the time being, as the only currently existing hardware using it are the Renoir APUs. Therefore, until this is testable and can be fixed properly, at least make sure the build will not fail. Signed-off-by:
Daniel Kolesa <daniel@octaforge.org> Signed-off-by:
-
James Zhu authored
Support pause_state for multiple instance, and it will fix vcn2.5 DPG mode power off issue on instance 1. Signed-off-by:
-
Evan Quan authored
SMU FW will handle the features disablement for baco reset on Arcturus. Signed-off-by:
-
Jack Zhang authored
For sriov and pp_onevf_mode, do not send message to set smu status, because smu doesn't support these messages under VF. Besides, it should skip smu_suspend when pp_onevf_mode is disabled. Signed-off-by:
-
- 06 Feb, 2020 5 commits
-
-
Takashi Iwai authored
Currently, gcc spews a warning as: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hubbub.c: In function ‘hubbub1_verify_allow_pstate_change_high’: ./include/drm/drm_print.h:316:2: warning: ‘debug_data’ may be used uninitialized in this function [-Wmaybe-uninitialized] This is because the code checks against a static value although it's basically a constant and guaranteed to be set. This patch changes the type prefix from static to const for addressing the compile warning above and also for letting the compiler optimize better. Fixes: 62d591a8 ("drm/amd/display: create new files for hubbub functions") Reviewed-by:
Takashi Iwai <tiwai@suse.de> Signed-off-by:
-
Amber Lin authored
Provide compute queues information in sysfs under /sys/class/kfd/kfd/proc. The format is /sys/class/kfd/kfd/proc/<pid>/queues/<queue id>/XX where XX are size, type, and gpuid three files to represent queue size, queue type, and the GPU this queue uses. <queue id> folder and files underneath are generated when a queue is created. They are removed when the queue is destroyed. Signed-off-by:
Amber Lin <Amber.Lin@amd.com> Reviewed-by:
-
Joseph Gravenor authored
[why] not turning off the mst hub before detection on reboot causes us to not be able to light up displays with mst hook [how] on hw init, see if any displays are lit up. if so, turn them off Signed-off-by:
Joseph Gravenor <joseph.gravenor@amd.com> Reviewed-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
-
Isabel Zhang authored
[Why] Starting from 14nm, the PLL is built into the PHY and the PLL is mapped to PHY on 1 to 1 basis. In the code, the DP port is mapped to a PLL that was not initialized. This causes DP to HDMI dongle to not light up the display. [How] Initializations added for PLL2 when creating resources. Signed-off-by:
Isabel Zhang <isabel.zhang@amd.com> Reviewed-by:
-
Tony Cheng authored
[Why] these registers should have been double buffered. SW workaround we will have SW program the more aggressive (lower) values whenever we are upating this register, so we will not have underflow at expense of less optimzal request pattern. [How] there is a driver bug where we don't check for 0, which is uninitialzed HW default. since 0 is smaller than any value we need to program, driver end up with not programming these registers Signed-off-by:
Tony Cheng <tony.cheng@amd.com> Reviewed-by:
-
