- 21 Dec, 2011 40 commits
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Ben Skeggs authored
Signed-off-by:Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
This area is horrifically complicated on these chipsets, and it's likely we will need at least a few more tweaks yet. Oh yes, and it's completely disabled on IGPs for the moment. From traces, things look potentially different there yet again. Sigh... Signed-off-by: -
Martin Peres authored
Following to "drm/nv50/pm: s/unk05/vdec/", let's rename the PLL to PLL_VDEC PLL names are purely indicative and are based on the most important engine it clocks. Signed-off-by:
Martin Peres <martin.peres@labri.fr> Signed-off-by:
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Martin Peres authored
Reporting an error is better than silently refusing to reclock. V2: Use the same logic on nv40 Signed-off-by:
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Martin Peres authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
This hasn't been necessary for a long time now.. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
Fixes a case where we don't get separate supervisor interrupt sequences for disconnect and modeset events. Signed-off-by: -
Ben Skeggs authored
Should fix issues with kexec, and as a nice side bonus, the code to avoid having PDISP disappear will also fix hibernate on those effected systems. Signed-off-by: -
Ben Skeggs authored
This has the effect of ensuring the encoders which were active before we loaded get disconnected properly before we start reprogramming them. Also removing a bit of cargo-cult from the initial evo pushbuf. Signed-off-by: -
Ben Skeggs authored
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Maxim Levitsky authored
PDISP doesn't like it when disabled CRTCs are poked. Fixes external output not coming to life when it has cursor on. https://bugs.freedesktop.org/show_bug.cgi?id=41608Signed-off-by:
Maxim Levitsky <maximlevitsky@gmail.com> Signed-off-by:
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Maxim Levitsky authored
Otherwice code that responsible for idling the card can't work. BIOS init tables are supposed to init the clocks to correct values, so that shouldn't cause any problems (we don't reclock by default anyway) Signed-off-by:
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Maxim Levitsky authored
Because doing polling while hardware is disabled is a bad idea... Signed-off-by:
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Maxim Levitsky authored
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Ben Skeggs authored
Exposes the same connector properties as the Radeon implementation, however their behaviour isn't exactly the same. The primary difference being that unless both hborder/vborder have been defined by the user, the driver will keep the aspect ratio of the overscanned area the same as the mode the display is programmed for. Enabled for digital outputs on GeForce 8 and up, excluding GF119. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
Prevents EVO getting all angry at us. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
A NV49 appeared a while back that was using the "nv41 style" pwm registers, rather than the "nv40 style" ones my board is using. This disproves the previous theory that the pwm controller choice is chipset-specific. So, after looking at a bunch of vbios images it appears that the next viable theory is that we should select the pwm controller to use based on the gpio line the fan is tied to, just like we do on nv50. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
The handling of the internal pwm fan controller is similar enough between current chipsets that it makes sense to share the logic, and bugfixes :) No hw backends converted yet, will automatically fall-through to the "old" per-chipset fanspeed hooks for now. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
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Martin Peres authored
Exposes the following sysfs entries: - fan0_input: read the rotational speed of the fan (poll a bit during 250ms) - pwm0: set the pwm duty cycle - pwm0_min/max: set the minimum/maximum pwm value v2 (Ben Skeggs): - nv50 pwm controller code removed in favour of other more complete code - FAN_RPM -> FAN_SENSE - merged FAN_SENSE readout into common code, not at all nv50-specific - protected fanspeed changes with perflvl_wr - formatting tidying - added some comments where things are shaky v3 (Martin Peres) - ensure duty min/max from thermal table are sane Signed-off-by:
Martin Peres <martin.peres@ensi-bourges.fr>
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Ben Skeggs authored
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Ben Skeggs authored
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