- 07 Jan, 2020 5 commits
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Dhinakaran Pandiyan authored
Gen-12 display can decompress surfaces compressed by the media engine, add a new modifier as the driver needs to know the surface was compressed by the media or render engine. v2: Update code comment describing the color plane order for YUV semiplanar formats. Cc: Nanley G Chery <nanley.g.chery@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Cc: dri-devel@lists.freedesktop.org Signed-off-by:Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Signed-off-by:
Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:
Imre Deak <imre.deak@intel.com> Reviewed-by:
Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191231233756.18753-6-imre.deak@intel.com
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Imre Deak authored
As intel_fb_plane_get_subsampling() returns the subsampling factor wrt. its main plane, for a CCS plane we need to apply both the main and the CCS plane's subsampling factor on the FB's dimensions to get the CCS plane's dimensions. Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
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Imre Deak authored
Print a debug message if the FB plane[0] offset is not 0 as expected, to help understainding an add FB IOCTL fail. Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by:
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Imre Deak authored
Currently the GGTT offset of a UV plane in a semiplanar YUV FB is tile size (4kB) aligned. I noticed, that enforcing only this alignment leads oddly to random memory corruptions on TGL while scanning out Y-tiled FBs. This issue can be easily reproduced with a UV plane offset that is not aligned to the plane's tile row size. Some experiments showed the correct alignment to be tile row size indeed. This also makes sense, since the de-tiling fence created for the object - with its own stride and so "left" and "right" edge - applies to all the planes in the FB, so each tile row of all planes should be tile row aligned. In fact BSpec requires this alignment since SKL. On SKL we may enforce this due to the AUX plane x,y coords check, but on ICL and TGL we don't. For now enforce this only on TGL; I can follow up with any necessary change for ICL after more tests. BSpec requires a stricter alignment for linear UV planes too (kind of a tile row alignment), but it's unclear whether that's really needed (couldn't be explained with the de-tiling fence as above) and enforcing that could break existing user space; so avoid that too for now until more tests. v2: - Clarify the commit log wrt. the address space the alignment applies to. (Chris) Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by:
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Imre Deak authored
At least one framebuffer plane on TGL - the UV plane of YUV semiplanar FBs - requires a non-power-of-2 alignment, so add support for this. This new alignment restriction applies only to an offset within an FB, so the GEM buffer itself containing the FB must still be power-of-2 aligned. Add a check for this (in practice plane 0, since the plane 0 offset must be 0). v2: - Fix WARN check for alignment=0. v3: - Return error for alignment programming bugs. (Chris) Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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- 06 Jan, 2020 8 commits
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Kai Vehmanen authored
Revert changes done in commit f6ec9483 ("drm/i915: extend audio CDCLK>=2*BCLK constraint to more platforms"). Audio drivers communicate with i915 over HDA bus multiple times during system boot-up and each of these transactions result in matching get_power/put_power calls to i915, and depending on the platform, a modeset change causing visible flicker. GLK is the only platform with minimum CDCLK significantly lower than BCLK, and thus for GLK setting a higher CDCLK is mandatory. For other platforms, minimum CDCLK is close but below 2*BCLK (e.g. on ICL, CDCLK=176.4kHz with BCLK=96kHz). Spec-wise the constraint should be set, but in practise no communication errors have been reported and the downside if set is the flicker observed at boot-time. Revert to old behaviour until better mechanism to manage probe-time clocks is available. The full CDCLK>=2*BCLK constraint is still enforced at pipe enable time in intel_crtc_compute_min_cdclk(). Bugzilla: https://gitlab.freedesktop.org/drm/intel/issues/913 Fixes: f6ec9483 ("drm/i915: extend audio CDCLK>=2*BCLK constraint to more platforms") Signed-off-by:
Kai Vehmanen <kai.vehmanen@linux.intel.com> Reviewed-by:
Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
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Chris Wilson authored
Be sure to initialise the uabi_instance on the virtual engine to the special invalid value, just in case we ever peek at it from the uAPI. Reported-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Fixes: 750e76b4 ("drm/i915/gt: Move the [class][inst] lookup for engines onto the GT") Signed-off-by:
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Chris Wilson authored
Put memset_p to use to clear the array of pointers used for tracking the ELSP. Signed-off-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200106114234.2529613-6-chris@chris-wilson.co.uk
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Chris Wilson authored
The last remaining reason for serialising the pin/unpin of the intel_context is to ensure that our preallocated wakerefs are not consumed too early (i.e. the unpin of the previous phase does not emit the idle barriers for this phase before we even submit). All of the other operations within the context pin/unpin are supposed to be atomic... Therefore, we can reduce the serialisation to being just on the i915_active.preallocated_barriers itself and drop the nested pin_mutex from intel_context_unpin(). Signed-off-by:
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Chris Wilson authored
Convert the few remaining GEM_TRACE() used for debugging over to the appropriate GT_TRACE or RQ_TRACE. References: 639f2f24 ("drm/i915: Introduce new macros for tracing") Signed-off-by:
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Chris Wilson authored
As we already have a flags field buried within i915_request, reuse it! Signed-off-by:
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Chris Wilson authored
Avoid spinning indefinitely waiting for the request to be submitted, and instead apply a timeout. A secondary benefit is that the error message will show which suspect is blocked. Signed-off-by:
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Chris Wilson authored
The local var does not need the __user as it exists on the kernel stack and not a pointer into the __user address space. drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c:989:9: warning: dereference of noderef expression drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c:990:13: warning: dereference of noderef expression Signed-off-by:
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- 05 Jan, 2020 2 commits
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Ramalingam C authored
When LMEM is supported, dumb buffer preferred to be created from LMEM. v2: Parameters are reshuffled. [Chris] v3: s/region_id/mem_type v4: use the i915_gem_object_create_region [chris] Signed-off-by:
Ramalingam C <ramalingam.c@intel.com> cc: Matthew Auld <matthew.auld@intel.com> Reviewed-by:
Matthew Auld <matthew.auld@intel.com> Signed-off-by:
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Ramalingam C authored
Lookup function to retrieve the pointer to a memory region of a mem_type. v2: for_each_memory_region is used. Signed-off-by:
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- 04 Jan, 2020 3 commits
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Chris Wilson authored
Check that the user writes into their mmap are visible on the GPU. Signed-off-by:
Abdiel Janulgue <abdiel.janulgue@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200103204137.2131004-3-chris@chris-wilson.co.uk
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Abdiel Janulgue authored
Instead of testing individually our new fault handlers, iterate over all memory regions and test all from one interface. Signed-off-by:
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Abdiel Janulgue authored
Local memory objects are similar to our usual scatterlist, but instead of using the struct page stored therein, we need to use the sg->dma_address. Signed-off-by:
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- 03 Jan, 2020 13 commits
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Chris Wilson authored
Include the types used by the headers to they can be compiled standalone. Signed-off-by:
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Chris Wilson authored
Move the definition of the igt_atomic_section[] into a C file, leaving the declaration in the header so as not to upset headertest! Signed-off-by:
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Chris Wilson authored
Create a vmap for discontinguous lmem objects to support i915_gem_object_pin_map(). v2: Offset io address by region.start for fake-lmem Signed-off-by:
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Chris Wilson authored
Keep scrubbing the kernel_context image with poison before we reset it in order to demonstrate that we will be resilient in the case where it is accidentally overwritten on idle. Suggested-by:
Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200102131707.1463945-5-chris@chris-wilson.co.uk
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Chris Wilson authored
Before we idle, on parking, we switch to the kernel context such that we have a scratch context loaded while the GPU idle, protecting any precious user state. Be paranoid and assume that the idle state may have been trashed, and reset the kernel_context image after idling. Signed-off-by:
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Chris Wilson authored
We leave the kernel_context on the HW as we suspend (and while idle). There is no guarantee that is complete in memory, so we try to inhibit restoration from the kernel_context. Reinforce the inhibition by scrubbing the context. Signed-off-by:
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Chris Wilson authored
When creating the initial LRC image, we also want to clear the MI_NOOPs and register values. Rather than use a blanket memset beforehand, apply the clears inline, close the context image and force inhibition of the uninitialised reminder. Signed-off-by:
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Chris Wilson authored
Empirically the minimal context image we use for rcs is insufficient to state the engine. This is demonstrated if we poison the context image such that any uninitialised state is invalid, and so if the engine samples beyond our defined region, will fail to start. Signed-off-by:
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Hans de Goede authored
On Bay Trail devices the MIPI power on/off sequences for DSI LCD panels do not control the LCD panel- and backlight-enable GPIOs. So far, when the VBT indicates we should use the SoC for backlight control, we have been relying on these GPIOs being configured as output and driven high by the Video BIOS (GOP) when it initializes the panel. This does not work when the device is booted with a HDMI monitor connected as then the GOP will initialize the HDMI instead of the panel, leaving the panel black, even though the i915 driver tries to output an image to it. Likewise on some device-models when the GOP does not initialize the DSI panel it also leaves the mux of the PWM0 pin in generic GPIO mode instead of muxing it to the PWM controller. This commit makes the DSI code control the SoC GPIOs for panel- and backlight-enable on BYT, when the VBT indicates the SoC should be used for backlight control. It also ensures that the PWM0 pin is muxed to the PWM controller in this case. This fixes the LCD panel not lighting up on various devices when booted with a HDMI monitor connected. This has been tested to fix this on the following devices: Peaq C1010 Point of View MOBII TAB-P800W Point of View MOBII TAB-P1005W Terra Pad 1061 Yours Y8W81 Reviewed-by:
Linus Walleij <linus.walleij@linaro.org> Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191216205122.1850923-6-hdegoede@redhat.com
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Hans de Goede authored
Move the Crystal Cove PMIC panel GPIO lookup-table from drivers/mfd/intel_soc_pmic_core.c to the i915 driver. The moved looked-up table is adding a GPIO lookup to the i915 PCI device and the GPIO subsys allows only one lookup table per device, The intel_soc_pmic_core.c code only adds lookup-table entries for the PMIC panel GPIO (as it deals only with the PMIC), but we also need to be able to access some GPIOs on the SoC itself, which requires entries for these GPIOs in the lookup-table. Since the lookup-table is attached to the i915 PCI device it really should be part of the i915 driver, this will also allow us to extend it with GPIOs from other sources when necessary. Acked-by:
Andy Shevchenko <andriy.shevchenko@intel.com> Reviewed-by:
Lee Jones <lee.jones@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20191216205122.1850923-5-hdegoede@redhat.com
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Hans de Goede authored
When the LCD has not been turned on by the firmware/GOP, because e.g. the device was booted with an external monitor connected over HDMI, we should not turn on the panel-enable GPIO when we request it. Turning on the panel-enable GPIO when we request it, means we turn it on too early in the init-sequence, which causes some panels to not correctly light up. This commits adds a panel_is_on parameter to intel_dsi_vbt_gpio_init() and makes intel_dsi_vbt_gpio_init() set the initial GPIO value accordingly. This fixes the panel not lighting up on a Thundersoft TST168 tablet when booted with an external monitor connected over HDMI. Changes in v2: - Call intel_dsi_get_hw_state() to check if the panel is on instead of relying on the current_mode pointer Reviewed-by:
Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191216205122.1850923-4-hdegoede@redhat.com
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Hans de Goede authored
On some older devices (BYT, CHT) which may use v2 VBT MIPI-sequences, we need to manually control the panel enable GPIO as v2 sequences do not do this. So far we have been carrying the code to do this on BYT/CHT devices with a Crystal Cove PMIC in vlv_dsi.c, but as this really is a shortcoming of the VBT MIPI-sequences, intel_dsi_vbt.c is a better place for this, so move it there. This is a preparation patch for adding panel-enable and backlight-enable GPIO support for BYT devices where instead of the PMIC the SoC is used for backlight control. Reviewed-by:
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Chris Wilson authored
Synchronise with any background retires and parking we may have spawned, so that all requests are accounted for. Closes: https://gitlab.freedesktop.org/drm/intel/issues/878Signed-off-by:
Andi Shyti <andi.shyti@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200102231604.1669010-1-chris@chris-wilson.co.uk
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- 02 Jan, 2020 3 commits
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Chris Wilson authored
Small objects that only occupy a single page are naturally contiguous, so mark them as such and allow them the special abilities that come with it. A more thorough treatment would extend i915_gem_object_pin_map() to support discontiguous lmem objects, following the example of ioremap_prot() and use get_vm_area() + remap_io_sg(). Signed-off-by:
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Masahiro Yamada authored
I implemented a small build rule in drivers/gpu/drm/i915/Makefile without relying on the special header-test-y syntax that was removed in commit fcbb8461 ("kbuild: remove header compile test"). I excluded some headers from the test coverage. I hope somebody intrested can take a closer look at them. Dummy subdir Makefiles can be removed altogether as single target build use case is now covered by commit 394053f4 ("kbuild: make single targets work more correctly"). v2 by Jani: - add selftests/i915_perf_selftests.h to no-header-test - add .gitignore for *.hdrtest Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by:
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Jani Nikula authored
Merge branch 'ib-pinctrl-unreg-mappings' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl into drm-intel-next-queued Merge pincntrl to unblock further i915 changes on top by Hans. Signed-off-by:
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- 01 Jan, 2020 3 commits
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Chris Wilson authored
We use the global device inode, shared amongst all files, and not the user's device filp to provide the backing storage for the mmap. The vma->vm_file provides a redundant reference that breaks existing expected behaviour that closing the user's device fd will release the resources bound to it, if a mmap persists. (Even without the vma->vm_file, the mmap will persist past the user's fd as the storage is bound to the device, i.e. our reference is on the object not file.) Fixes: cc662126 ("drm/i915: Introduce DRM_I915_GEM_MMAP_OFFSET") Closes: https://gitlab.freedesktop.org/drm/intel/issues/919Signed-off-by:
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Matt Roper authored
The workaround database now indicates we need to disable psdunit clock gating as well. v3: - Rebase on top of other workarounds that have landed. - Restrict cc:stable tag to 5.2+ since that's when ICL was first officially supported. Bspec: 32354 Bspec: 33450 Bspec: 33451 Suggested-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: stable@vger.kernel.org # v5.2+ Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Matt Atwood <matthew.s.atwood@intel.com> Signed-off-by:
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Chris Wilson authored
The coarse power gating was disabled as part of commit 2248a283 ("drm/i915/gen8+: Add RC6 CTX corruption WA") as a prelude to recover from the context corruption; the power gating itself has no direct impact on the RC6 context corruption. However, that recovery scheme was never implemented due to difficult corner cases, and so we no longer need to keep the power gating disabled. Fixes: 2248a283 ("drm/i915/gen8+: Add RC6 CTX corruption WA") Closes: https://gitlab.freedesktop.org/drm/intel/issues/846Signed-off-by:
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- 31 Dec, 2019 3 commits
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Abdiel Janulgue authored
Provide a way to set the PTE within apply_page_range for discontiguous objects in addition to the existing method of just incrementing the pfn for a page range. Fixes: cc662126 ("drm/i915: Introduce DRM_I915_GEM_MMAP_OFFSET") Signed-off-by:
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Matt Roper authored
Our usual i915 convention is to assume that future platforms will follow the same behavior as the latest platform of today. The VDBOX/SFC capabilities described here don't seem like something that should be specific to TGL, so let's future-proof by making the test apply to all gen12+ platforms. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:
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Chris Wilson authored
A small tweak to flush then invalidate appears to improve the reliability of ppGTT switches on Ivybridge -- but does not improve hsw/vlv bcs reliability. Signed-off-by:
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