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- 18 Jul, 2019 2 commits
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Le Ma authored
Add common IP blocks for Arcturus. Signed-off-by:
Le Ma <le.ma@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Le Ma authored
Add support for the IP offsets on Arcturus. Signed-off-by:
Le Ma <le.ma@amd.com> Acked-by: Snow Zhang < Snow.Zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 16 Jul, 2019 2 commits
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Arnd Bergmann authored
It is annoying to have #warnings that trigger in randconfig builds like drivers/gpu/drm/amd/amdgpu/soc15.c:653:3: error: "Enable CONFIG_DRM_AMD_DC for display support on SOC15." drivers/gpu/drm/amd/amdgpu/nv.c:400:3: error: "Enable CONFIG_DRM_AMD_DC for display support on navi." Remove these and rely on the users to turn these on. Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Kent Russell authored
The perf counter for Vega20 is 108, instead of 104 which it was on all previous GPUs, so add a check to use the appropriate value. Signed-off-by:
Kent Russell <kent.russell@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 25 Jun, 2019 1 commit
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Ernst Sjöstrand authored
Reported by smatch: drivers/gpu/drm/amd/amdgpu/soc15.c:715 soc15_get_pcie_usage() warn: inconsistent indenting And a similar one in si.c. Signed-off-by:
Ernst Sjöstrand <ernstp@gmail.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 21 Jun, 2019 2 commits
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Hawking Zhang authored
Since from soc15, make sure only AndMasked bit get changed when applied or_mask Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Le Ma <Le.Ma@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Hawking Zhang authored
Move to the header file. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 20 Jun, 2019 1 commit
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Jonathan Kim authored
add pmu attribute groups and structures for perf events. add sysfs to track available df perfmon counters fix overflow handling in perfmon counter reads. v2: squash in fix (Alex) Signed-off-by:
Jonathan Kim <Jonathan.Kim@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 10 Jun, 2019 1 commit
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Sam Ravnborg authored
With this commit drm/amd/ has no longer any uses of the deprecated drmP.h header file. Signed-off-by:
Sam Ravnborg <sam@ravnborg.org> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20190609220757.10862-11-sam@ravnborg.org
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- 28 May, 2019 2 commits
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Emily Deng authored
For passthrough, after rebooted the VM, driver will do a baco reset before doing other driver initialization during loading driver. For doing the baco reset, it will first check the baco reset capability. So first need to set the cap from the vbios information or baco reset won't be enabled. Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Not necessary on soc15 and breaks driver reload on server cards. Acked-by:
Amber Lin <Amber.Lin@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 24 May, 2019 6 commits
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Alex Deucher authored
If RAS or XGMI are enabled, you have to use mode1 reset rather than BACO. Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Trigger Huang authored
Under Vega10 SR-IOV, with new RLC's new feature, VF should call RLC to program some registers if supported Signed-off-by:
Trigger Huang <Trigger.Huang@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Trigger Huang authored
For Vega10 SR-IOV VF, skip setting some regs due to: 1, host will program them 2, avoid VF register programming violations Signed-off-by:
Trigger Huang <Trigger.Huang@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Trigger Huang authored
In order to support new PSP feature that PSP may provide interface to program IH CNTL register, initialize PSP before IH under Vega10 SR-IOV VF Signed-off-by:
Trigger Huang <Trigger.Huang@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Kent Russell authored
Add a sysfs file for reporting the number of PCIe replays (NAKs). This returns the sum of NAKs received and NAKs generated Signed-off-by:
Kent Russell <kent.russell@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Oak Zeng authored
Remap HDP_MEM_COHERENCY_FLUSH_CNTL and HDP_REG_COHERENCY_FLUSH_CNTL to an empty page in mmio space. We will later map this page to process space so application can flush hdp. This can't be done properly at those registers' original location because it will expose more than desired registers to process space. v2: Use explicit register hole location v3: Moved remapped hdp registers into adev struct v4: Use more generic name for remapped page Expose register offset in kfd_ioctl.h v5: Move hdp register remap function to nbio ip function v6: Fixed operator precedence issue and other bugs Signed-off-by:
Oak Zeng <Oak.Zeng@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 20 May, 2019 1 commit
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Alex Deucher authored
Not necessary on soc15 and breaks driver reload on server cards. Acked-by:
Amber Lin <Amber.Lin@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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- 19 Apr, 2019 2 commits
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Likun Gao authored
Enable MGCG for picasso. Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Evan Quan authored
PSP SOS firmware needs to be 0x80067 or later. Signed-off-by:
Evan Quan <evan.quan@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 28 Mar, 2019 1 commit
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Evan Quan authored
The error return value should be correctly reflected. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 19 Mar, 2019 4 commits
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Evan Quan authored
Applied vdci flush workaround for Vega20 BACO. Signed-off-by:
Evan Quan <evan.quan@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Likun Gao authored
Move pp_feature from the struct of amd_powerplay to amdgpu_device. Add pp_feature limit for overdrive interface. v2: put pp_feature into struct amdgpu_pm. v3: merge feature_mask with pp_feature. Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
Kevin Wang <kevin1.wang@amd.com> Suggested-by:
Alex Deucher <alexander.deucher@amd.com> Suggested-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Kevin Wang authored
add this helper to check new sw-smu support. Signed-off-by:
Kevin Wang <Kevin1.Wang@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Huang Rui authored
Switch to new smu ip block since vega20. Signed-off-by:
Huang Rui <ray.huang@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 05 Mar, 2019 1 commit
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Alex Deucher authored
Use BACO for reset of the platform supports it. Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 28 Feb, 2019 1 commit
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Candice Li authored
This reverts commit 2172b89e. Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 01 Feb, 2019 1 commit
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Huang Rui authored
This patch fixes the incorrect external id that kernel reports to user mode driver. Raven2's rev_id is starts from 0x8, so its external id (0x81) should start from rev_id + 0x79 (0x81 - 0x8). And Raven's rev_id should be 0x21 while rev_id == 1. Reported-by:
Crystal Jin <Crystal.Jin@amd.com> Signed-off-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 25 Jan, 2019 5 commits
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Evan Quan authored
So that we do not need to check this in every internal function. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Oak Zeng authored
HW doorbell writing routing policy: writing to doorbell not in SDMA/IH/MM/ACV doorbell range will be routed to CP. So CP doorbell routing depends on doorbell range setting of above blocks. Setting doorbell range of above blocks earlier (soc15_common_hw_init) to make sure CP doorbell writing be routed to CP block. Signed-off-by:
Oak Zeng <Oak.Zeng@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Rather than just -1. Reviewed-by:
JimQu <Jim.Qu@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Jim Qu authored
Signed-off-by:
Jim Qu <Jim.Qu@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Jim Qu authored
It will fall back to use mode1 reset if platform does not support BACO feature. v2: squash in warning fix (Alex) Signed-off-by:
Jim Qu <Jim.Qu@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 14 Jan, 2019 2 commits
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Alex Deucher authored
SOC15 chips require a reset if the driver was previously loaded because the PSP can only be loaded once between each reset. v2: rebase, handle multiple asic funcs Reviewed-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Kent Russell authored
Add a sysfs file that reports the number of bytes transmitted and received in the last second. This can be used to approximate the PCIe bandwidth usage over the last second. v2: Clarify use of mps as estimation of bandwidth v3: Don't make the file on APUs v4: Early exit for APUs in the read function, change output to display "packets-received packets-sent mps" v5: fix missing header for si (Alex) Signed-off-by:
Kent Russell <kent.russell@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 03 Dec, 2018 1 commit
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Alex Deucher authored
Use this to track whether an asic supports xgmi rather than checking the asic type everywhere. Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 28 Nov, 2018 2 commits
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Oak Zeng authored
This introduces new doorbell layout for vega20 and future asics v2: Use enum definition instead of hardcoded value Signed-off-by:
Oak Zeng <ozeng@amd.com> Suggested-by:
Felix Kuehling <Felix.Kuehling@amd.com> Suggested-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Oak Zeng authored
v2: Use enum definition instead of hardcoded value v3: Remove unused enum definition Signed-off-by:
Oak Zeng <ozeng@amd.com> Suggested-by:
Felix Kuehling <Felix.Kuehling@amd.com> Suggested-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 20 Nov, 2018 1 commit
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Kenneth Feng authored
Due to the register name and setting change of HDP memory light sleep on Vega20,change accordingly in the driver. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 10 Oct, 2018 1 commit
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Rex Zhu authored
initialize gfx/sdma before dpm features enabled. Acked-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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