- 24 Sep, 2010 40 commits
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Cyril Chemparathy authored
This patch adds support for tnetv107x's on-chip touchscreen controller. Signed-off-by:
Cyril Chemparathy <cyril@ti.com> Acked-by:
Dmitry Torokhov <dtor@mail.ru> Signed-off-by:
Kevin Hilman <khilman@deeprootsystems.com>
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Cyril Chemparathy authored
This patch adds evm board specific keymap definitions and controller configuration data for on-chip keypad controller on tnetv107x silicon. Signed-off-by:
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Cyril Chemparathy authored
This patch adds a platform device definition for tnetv107x's keypad controller. Signed-off-by:
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Cyril Chemparathy authored
This patch adds support for tnetv107x's on-chip keypad controller. Signed-off-by:
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Cyril Chemparathy authored
Having switched over to the newly introduced cpdma layer, this patch now removes a whole bunch of code that is now unused. This patch has been maintained separate strictly for reasons of readability. Signed-off-by:
David S. Miller <davem@davemloft.net> Tested-by:
Michael Williamson <michael.williamson@criticallink.com> Tested-by:
Caglar Akyuz <caglarakyuz@gmail.com> Signed-off-by:
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Cyril Chemparathy authored
This patch hooks up the emac driver with the newly separated cpdma driver. Key differences introduced here: - The old buffer list scheme is no longer required - The original code maintained mac address per rx channel, even if only one rx channel was being used. With this change, mac address is maintained device wide. If support for multiple rx channels is added in future, this will need to be reworked a bit. - The new CPDMA code handles short packets better than before. The earlier code was adjusting the length up, without ensuring that the tail end of the padding was cleared - a possible security issue. This has been fixed to use skb_padto(). Signed-off-by:
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Cyril Chemparathy authored
In addition to being embedded into the EMAC controller, the CPDMA hardware block is used in TI's CPSW switch controller. Fortunately, the programming interface to this hardware block remains pretty nicely consistent across these devices. This patch adds a new CPDMA services layer, which can then be reused across EMAC and CPSW drivers. Signed-off-by:
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Cyril Chemparathy authored
This patch removes code that has been rendered useless by the previous patches in this series. Signed-off-by:
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Cyril Chemparathy authored
This patch removes davinci architecture code that has now been rendered useless by the previous patches in the MDIO separation series. Signed-off-by:
Tony Lindgren <tony@atomide.com> Signed-off-by:
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Cyril Chemparathy authored
This patch removes davinci architecture code that has now been rendered useless by the previous patches in the MDIO separation series. In addition, the earlier phy_mask definitions have been replaced with corresponding phy_id definitions. Signed-off-by:
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Cyril Chemparathy authored
This patch switches the emac implementation over to the newly separated MDIO driver. With this, the mdio bus frequency defaults to a safe 2.2MHz. Boards may optionally specify a bus frequency via platform data. The phy identification scheme has been modified to use a phy bus id instead of a mask. This largely serves to eliminate the "phy search" code in emac init. Signed-off-by:
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Cyril Chemparathy authored
This patch adds mdio platform devices on SoCs that have the necessary hardware. Clock lookup entries (aliases) have also been added, so that the MDIO and EMAC drivers can independently enable/disable a shared underlying clock. Further, the EMAC MMR region has been split down into separate MDIO and EMAC regions. Signed-off-by:
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Cyril Chemparathy authored
This patch adds mdio platform devices on SoCs that have the necessary hardware. Clock lookup entries (aliases) have also been added, so that the MDIO and EMAC drivers can independently enable/disable a shared underlying clock. Further, the EMAC MMR region has been split down into separate MDIO and EMAC regions. Signed-off-by:
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Cyril Chemparathy authored
Davinci's MDIO controller is present on other TI devices, without an accompanying EMAC. For example, on tnetv107x, the same MDIO module is used in conjunction with a 3-port switch hardware. By separating the MDIO controller code into its own platform driver, this patch allows common logic to be reused on such platforms. Signed-off-by:
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Michael Williamson authored
This patch adds the i2c0 bus and attached devices to the MityDSP-L138 and MityARM-1808 davinci SoM. Included is a TPS65023 voltage regulator needed for power management and a small 24c02 EPROM that contains factory configuration data. Signed-off-by:
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Cyril Chemparathy authored
This patch adds an entry into the idcode table for tnetv107x silicon revision 1.1 and 1.2 devices. Signed-off-by:
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Michael Williamson authored
This patch adds initial support for the MityDSP-L138 and MityDSP-1808 system on Module (SOM) under the machine name "mityomapl138". These SOMs are based on the da850 davinci CPU architecture. Information on these SOMs may be found at http://www.mitydsp.com. Basic support for the console UART, NAND, and EMAC (MII interface) is included in this patch. Signed-off-by:
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Michael Williamson authored
In order to support reference DA8XX machines not providing a voltage regulator control for the core voltage, the REGULATOR_DUMMY option is required. Signed-off-by:
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Michael Williamson authored
This patch adds machine checks in the serial console init routines for the DA8XX EVM boards. This is needed because there are other DA8XX based machines that use a different UART/tty as the console and may be included in a common kernel build. Signed-off-by:
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Sekhar Nori authored
Setup NAND flash timing on DM6467T EVM. Without the timing setup, the NAND flash on DM6467T RevC EVM reports a number of random bad blocks because of read errors. Also, with this, copying a 100M file on RevB EVM takes ~35 sec against 1 minute 30 seconds earlier. Signed-off-by:
Sekhar Nori <nsekhar@ti.com> Acked-by:
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Sekhar Nori authored
Setup the NAND flash timings for DA850 EVM Before configuring the timing values, throughput calculation using dd command yielded 469 kB/s write and 966 kB/s read speed. After the timing configuration, the throughput was measured to be 2.4 MB/s write and 5 MB/s read. [Mukul Bhatnagar: actual calculation of timing values from the NAND datasheet] Signed-off-by:
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Sudhakar Rajashekhara authored
Setup the NAND flash timings for DA830 EVM. Before configuring the timing values, throughput calculation using dd command yielded 477 kB/s write and 970 kB/s read speed. After the timing configuration, the throughput was measured to be 2.5 MB/s write and 5.1 MB/s read. [Mukul Bhatnagar: actual calculation of timing values from the NAND datasheet] Signed-off-by:
Sudhakar Rajashekhara <sudhakar.raj@ti.com> Cc: Mukul Bhatnagar <mbhatnagar@ti.com> Signed-off-by:
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Sekhar Nori authored
The DM644x EVM nand flash timing was earlier being done as a special case in the NAND driver itself. With the NAND driver now capable of progamming the AEMIF interface using timing data passed from the platform, the timing values are being moved into their rightful place in the EVM specific board file. The values being programmed match what was being done earlier and thus do not represent any change in performance/functionality. Signed-off-by:
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Sekhar Nori authored
This patch modifies the DaVinci NAND driver to use the new AEMIF timing setup API to configure the NAND access timings. Earlier, AEMIF configuration was being done as a special case for DM644x board, but now more boards emerge which have capability to boot for other media (SPI flash, NOR flash) and have the kernel access NAND flash. This means that kernel cannot always depend on the bootloader to setup the NAND. Also, on platforms such as da850/omap-l138, the aemif input frequency changes as cpu frequency changes; necessiating re-calculation of timimg values as part of cpufreq transtitions. This patch forms the basis for adding that support. Signed-off-by:
Artem Bityutskiy <Artem.Bityutskiy@nokia.com>
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Sekhar Nori authored
This patch adds support to configure the AEMIF interface with supplied timing values. Since this capability is useful both from NOR and NAND flashes, it is provided as a new interface and in a file of its own. AEMIF timing configuration is required in cases: 1) Where the AEMIF clock rate can change at runtime (a side affect of cpu frequency change). 2) Where U-Boot does not support NAND/NOR but supports other media like SPI Flash or MMC/SD and thus does not care about setting up the AEMIF timing for kernel to use. 3) Where U-Boot just hasn't configured the timing values and cannot be upgraded because the box is already in the field. Since there is now a header file for AEMIF interface, the common (non-NAND specific) defines for AEMIF registers have been moved from nand.h into the newly created aemif.h Signed-off-by:
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Sekhar Nori authored
By default the audio driver uses EDMAQ_0 as the DMA queue, but on DM365 this queue is specially designed for video transfers with a large fifo size. Having both audio and video transfers on the same queue leads to noise on the audio side. This patch changes the audio queue number for DM365 to EDMAQ_3. Signed-off-by:
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Juha Kuikka authored
Add resources, platform device and convenience registration function for DA850's second MMC/SD controller (MMCSD1). Signed-off-by:
Juha Kuikka <juha.kuikka@elektrobit.com> Signed-off-by:
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Juha Kuikka authored
Split mmcsd_clk into mmcsd0_clk and mmcsd1_clk and add davinci_mmc.1 in preparation for adding support for MMCSD1 peripheral in DA850. Signed-off-by:
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Juha Kuikka authored
Add LPSC id for DA850's MMCSD1 peripheral. Signed-off-by:
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Kulikov Vasiliy authored
If irq2ctlr() fails return IRQ_NONE. Also as it can fail make 'ctlr' signed. The semantic patch that finds this problem (many false-positive results): (http://coccinelle.lip6.fr/) // <smpl> @ r1 @ identifier f; @@ int f(...) { ... } @@ identifier r1.f; type T; unsigned T x; @@ *x = f(...) ... *x > 0 Signed-off-by:
Kulikov Vasiliy <segooon@gmail.com> Signed-off-by:
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Sergei Shtylyov authored
The CPGMAC pin list in da850.c was incorrectly split into two MII/RMII mode specific pin lists, while what pin group is used is a function of how the board is wired. Copy the pin lists to board-da850-evm.c, renaming them accordingly, and merge the two lists in da850.c into one, da850_cpgmac_pins[], representing the CPGMAC module as a whole... Signed-off-by:
Sergei Shtylyov <sshtylyov@ru.mvista.com> Tested-by:
Ben Gardiner <bengardiner@nanometrics.ca> Signed-off-by:
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Sergei Shtylyov authored
The NAND/NOR flash pin lists (da850_nand_pins/da850_nor_pins) are purely board specific and as such shouldn't be in da850.c -- copy them to board-da850-evm.c, renaming to da850_evm_nand_pins/da850_evm_nor_pins respectively, and merge the two lists in da850.c into one, representing the EMIF 2.5 module as a whole, just like we have it in da830.c... While at it, remove the '__init' modifier from da850_evm_setup_nor_nand() as this function is called from non '__init' code... Signed-off-by:
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Cyril Chemparathy authored
This is a bugfix for the original tnetv107x submission series. The psc_regs base array was being discarded post-init, and this was causing a crash during post-init clock enable/disable. Signed-off-by:
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Sekhar Nori authored
Keep PLL0 SYSCLK3 at a constant rate of 100MHz. This enables the AEMIF timing to remain valid even as the PLL0 output is changed by cpufreq driver to save power. Signed-off-by:
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Sekhar Nori authored
On OMAP-L138 SoC, some of the sysclks need not be at a fixed ratio to CPU clock and can be kept at a relatively constant rate by adjusting the PLLDIVn ratio even as cpufreq goes ahead and changes the CPU clock. This feature can be used to keep the EMIFA (PLL0 SYSCLK3) clock at a constant rate so that the EMIF timings need not be re-programmed whenever the CPU frequency changes. This patch adds the required suppport to cpufreq driver. Signed-off-by:
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Sekhar Nori authored
Setting sysclk rate will be useful in cases where the sysclk is not at a fixed ratio to the PLL output but can asynchronously be changed. This support forms the basis of attempt to keep the AEMIF clock constant on OMAP-L138 even as PLL0 output changes as ARM clock is changed to save power. This patch has been tested on OMAP-L138. Signed-off-by:
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Sekhar Nori authored
This patch disables internal pulldowns for all MMC/SD1 pins. Presently only MMCSD1_CMD pin's pull down is disabled, but with this some MMC/SD cards do not get detected on MMC/SD1 slot of the EVM. The problem was reproducible with SanDisk 4GB SDHC card. Reported-by:
Stephane Bovagne <s-bovagne@ti.com> Signed-off-by:
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Sekhar Nori authored
For each DA850 OPP, the normal ('NOM') voltage defined in the tecnical reference manual (TRM) is actually the minimum voltage the frequency is supported at. The minimum ('MIN') voltage defined in TRM is meant to take care of voltage fluctuations and the device should not be run at this voltage for extended periods of time. Fix the OPP definitions to define the cvdd_min as the normal voltage defined in the datasheet. Signed-off-by: -
Sekhar Nori authored
The Sitara AM17x SoCs from TI are an OMAP-L137 pin-to-pin compatible ARM9 microprocessor offering from TI. The Sitara AM18x SoCs from TI are an OMAP-L138 pin-to-pin compatible ARM9 microprocessor offering from TI. More information about these processors available at: www.ti.com/am1x Because of their compatibiliy with OMAP-L1x, the kernel support for OMAP-L1x is fully relevant to AM1x processors. This patch updates the Kconfig prompt and help text to include the AM1x part names to help users select configurations required for these parts easily. Also, the hardware information that shows up in /proc/cpuinfo is updated to show applicability of the respective OMAP-L1x EVMs for AM1x parts. Signed-off-by:
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Sekhar Nori authored
In arch/arm/mach-davinci/Kconfig, some of the configuration items are indented with multiple spaces instead of tabs. Also, in couple of places, two spaces are used in the middle of help text where one should do. This patch fixes both issues. Signed-off-by:
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