1. 24 Jan, 2016 31 commits
  2. 22 Jan, 2016 4 commits
    • Huacai Chen's avatar
      MIPS: hpet: Choose a safe value for the ETIME check · 5610b125
      Huacai Chen authored
      This patch is borrowed from x86 hpet driver and explaind below:
      
      Due to the overly intelligent design of HPETs, we need to workaround
      the problem that the compare value which we write is already behind
      the actual counter value at the point where the value hits the real
      compare register. This happens for two reasons:
      
      1) We read out the counter, add the delta and write the result to the
         compare register. When a NMI hits between the read out and the write
         then the counter can be ahead of the event already.
      
      2) The write to the compare register is delayed by up to two HPET
         cycles in AMD chipsets.
      
      We can work around this by reading back the compare register to make
      sure that the written value has hit the hardware. But that is bad
      performance wise for the normal case where the event is far enough in
      the future.
      
      As we already know that the write can be delayed by up to two cycles
      we can avoid the read back of the compare register completely if we
      make the decision whether the delta has elapsed already or not based
      on the following calculation:
      
        cmp = event - actual_count;
      
      If cmp is less than 64 HPET clock cycles, then we decide that the event
      has happened already and return -ETIME. That covers the above #1 and #2
      problems which would cause a wait for HPET wraparound (~306 seconds).
      Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
      Cc: Aurelien Jarno <aurelien@aurel32.net>
      Cc: Steven J. Hill <Steven.Hill@imgtec.com>
      Cc: Fuxin Zhang <zhangfx@lemote.com>
      Cc: Zhangjin Wu <wuzhangjin@gmail.com>
      Cc: Huacai Chen <chenhc@lemote.com>
      Cc: linux-mips@linux-mips.org
      Cc: stable@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/12162/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      5610b125
    • Huacai Chen's avatar
      MIPS: Loongson-3: Fix SMP_ASK_C0COUNT IPI handler · 57548432
      Huacai Chen authored
      When Core-0 handle SMP_ASK_C0COUNT IPI, we should make other cores to
      see the result as soon as possible (especially when Store-Fill-Buffer
      is enabled). Otherwise, C0_Count syncronization makes no sense.
      
      BTW, array is more suitable than per-cpu variable for syncronization,
      and there is a corner case should be avoid: C0_Count of Core-0 can be
      really 0.
      Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
      Cc: Aurelien Jarno <aurelien@aurel32.net>
      Cc: Steven J. Hill <Steven.Hill@imgtec.com>
      Cc: Fuxin Zhang <zhangfx@lemote.com>
      Cc: Zhangjin Wu <wuzhangjin@gmail.com>
      Cc: Huacai Chen <chenhc@lemote.com>
      Cc: linux-mips@linux-mips.org
      Cc: <stable@vger.kernel.org>
      Patchwork: https://patchwork.linux-mips.org/patch/12160/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      57548432
    • Huacai Chen's avatar
      MIPS: Loongson-3: Improve -march option and move it to Platform · 5188129b
      Huacai Chen authored
      If GCC >= 4.9 and Binutils >=2.25, we use -march=loongson3a, otherwise
      we use -march=mips64r2, this can slightly improve performance. Besides,
      arch/mips/loongson64/Platform is a better location rather than arch/
      mips/Makefile.
      Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
      Cc: Aurelien Jarno <aurelien@aurel32.net>
      Cc: Steven J. Hill <Steven.Hill@imgtec.com>
      Cc: Fuxin Zhang <zhangfx@lemote.com>
      Cc: Zhangjin Wu <wuzhangjin@gmail.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/12161/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      5188129b
    • Huacai Chen's avatar
      MIPS: Cleanup the unused __arch_local_irq_restore() function · 6e526844
      Huacai Chen authored
      In history, __arch_local_irq_restore() is only used by SMTC. However,
      SMTC support has been removed since 3.16, this patch remove the unused
      function.
      Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
      Cc: Aurelien Jarno <aurelien@aurel32.net>
      Cc: Steven J. Hill <Steven.Hill@imgtec.com>
      Cc: Fuxin Zhang <zhangfx@lemote.com>
      Cc: Zhangjin Wu <wuzhangjin@gmail.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/12159/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      6e526844
  3. 19 Jan, 2016 5 commits
    • Maciej W. Rozycki's avatar
      MIPS: Add IEEE Std 754 conformance mode selection · 503943e0
      Maciej W. Rozycki authored
      Add an `ieee754=' kernel parameter to control IEEE Std 754 conformance
      mode.
      
      Use separate flags copied from the respective CPU feature flags, and
      adjusted according to the conformance mode selected, to make binaries
      requesting individual NaN encoding modes accepted or rejected as needed.
      Update the initial setting for FCSR and, in the full FPU emulation mode,
      its read-only mask accordingly.  Accept the mode selection requested for
      legacy processors as well.
      
      As with the EF_MIPS_NAN2008 ELF file header flag adjust both ABS2008 and
      NAN2008 bits at the same time, to match the choice made for hardware
      currently implemented.
      Signed-off-by: default avatarMaciej W. Rozycki <macro@imgtec.com>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/11481/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      503943e0
    • Maciej W. Rozycki's avatar
      MIPS: Determine the presence of IEEE Std 754-2008 features · 93adeaf6
      Maciej W. Rozycki authored
      Determine the presence of and the amount of control available over IEEE
      Std 754-2008 features.
      
      In the case of a hardware FPU being used examine the FIR register for
      the presence of the HAS2008 bit and then the FCSR register for the
      writability of the ABS2008 and NAN2008 bits and the hardwired state of
      each of these bits if read-only.  Update the initial FCSR contents used
      for threads and the FCSR writability mask accordingly.
      
      For full FPU emulation and MIPS32 or MIPS64 processors make the FCSR
      ABS2008 and NAN2008 bits writable.
      Signed-off-by: default avatarMaciej W. Rozycki <macro@imgtec.com>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/11480/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      93adeaf6
    • Maciej W. Rozycki's avatar
      MIPS: ELF: Interpret the NAN2008 file header flag · 2b5e869e
      Maciej W. Rozycki authored
      Handle the EF_MIPS_NAN2008 ELF file header flag and refuse execution
      where there is no support in the FPU for the NaN encoding mode requested
      by a binary invoked.  Ensure that the setting of the bit in the binary
      matches one in any intepreter used.  Set the thread's initial FCSR
      contents according to the value of the EF_MIPS_NAN2008.
      
      Set the values of the FCSR ABS2008 and NAN2008 bits both to the same
      value if possible, to take the approach taken with existing FPU hardware
      into account.  As of now all implementations have both bits hardwired to
      the same value, that is both are fixed at 0 or both are fixed at 1, even
      though the architecture allows for implementations where the amount of
      control implemented with each of these two individual bits is
      independent of each other.
      Signed-off-by: default avatarMaciej W. Rozycki <macro@imgtec.com>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/11479/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      2b5e869e
    • Maciej W. Rozycki's avatar
      ELF: Also pass any interpreter's file header to `arch_check_elf' · eb4bc076
      Maciej W. Rozycki authored
      Also pass any interpreter's file header to `arch_check_elf' so that any
      architecture handler can have a look at it if needed.
      Signed-off-by: default avatarMaciej W. Rozycki <macro@imgtec.com>
      Acked-by: default avatarAndrew Morton <akpm@linux-foundation.org>
      Acked-by: default avatarAl Viro <viro@zeniv.linux.org.uk>
      Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/11478/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      eb4bc076
    • Maciej W. Rozycki's avatar
      MIPS: math-emu: Add IEEE Std 754-2008 NaN encoding emulation · 90d53a91
      Maciej W. Rozycki authored
      Implement IEEE Std 754-2008 NaN encoding wired to the state of the
      FCSR.NAN2008 bit.  Make the interpretation of the quiet bit in NaN data
      as follows:
      
      * in the legacy mode originally defined by the MIPS architecture the
        value of 1 denotes an sNaN whereas the value of 0 denotes a qNaN,
      
      * in the 2008 mode introduced with revision 5 of the MIPS architecture
        the value of 0 denotes an sNaN whereas the value of 1 denotes a qNaN,
        following the definition of the preferred NaN encoding introduced with
        IEEE Std 754-2008.
      
      In the 2008 mode, following the requirement of the said standard, quiet
      an sNaN where needed by setting the quiet bit to 1 and leaving all the
      NaN payload bits unchanged.
      
      Update format conversion operations according to the rules set by IEEE
      Std 754-2008 and the MIPS architecture.  Specifically:
      
      * propagate NaN payload bits through conversions between floating-point
        formats such that as much information as possible is preserved and
        specifically a conversion from a narrower format to a wider format and
        then back to the original format does not change a qNaN payload in any
        way,
      
      * conversions from a floating-point to an integer format where the
        source is a NaN, infinity or a value that would convert to an integer
        outside the range of the result format produce, under the default
        exception handling, the respective values defined by the MIPS
        architecture.
      
      In full FPU emulation set the FIR.HAS2008 bit to 1, however do not make
      any further FCSR bits writable.
      Signed-off-by: default avatarMaciej W. Rozycki <macro@imgtec.com>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/11477/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      90d53a91