1. 24 Mar, 2020 12 commits
  2. 23 Mar, 2020 3 commits
  3. 22 Mar, 2020 23 commits
  4. 20 Mar, 2020 2 commits
    • David S. Miller's avatar
      Merge tag 'mac80211-next-for-net-next-2020-03-20' of... · 0d7043f3
      David S. Miller authored
      Merge tag 'mac80211-next-for-net-next-2020-03-20' of git://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211-next
      
      Johannes Berg says:
      
      ====================
      Another set of changes:
       * HE ranging (fine timing measurement) API support
       * hwsim gets virtio support, for use with wmediumd,
         to be able to simulate with multiple machines
       * eapol-over-nl80211 improvements to exclude preauth
       * IBSS reset support, to recover connections from
         userspace
       * and various others.
      ====================
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      0d7043f3
    • Vladimir Oltean's avatar
      net: dsa: sja1105: Add support for the SGMII port · ffe10e67
      Vladimir Oltean authored
      SJA1105 switches R and S have one SerDes port with an 802.3z
      quasi-compatible PCS, hardwired on port 4. The other ports are still
      MII/RMII/RGMII. The PCS performs rate adaptation to lower link speeds;
      the MAC on this port is hardwired at gigabit. Only full duplex is
      supported.
      
      The SGMII port can be configured as part of the static config tables, as
      well as through a dedicated SPI address region for its pseudo-clause-22
      registers. However it looks like the static configuration is not
      able to change some out-of-reset values (like the value of MII_BMCR), so
      at the end of the day, having code for it is utterly pointless. We are
      just going to use the pseudo-C22 interface.
      
      Because the PCS gets reset when the switch resets, we have to add even
      more restoration logic to sja1105_static_config_reload, otherwise the
      SGMII port breaks after operations such as enabling PTP timestamping
      which require a switch reset.
      
      >From PHYLINK perspective, the switch supports *only* SGMII (it doesn't
      support 1000Base-X). It also doesn't expose access to the raw config
      word for in-band AN in registers MII_ADV/MII_LPA.
      It is able to work in the following modes:
       - Forced speed
       - SGMII in-band AN slave (speed received from PHY)
       - SGMII in-band AN master (acting as a PHY)
      
      The latter mode is not supported by this patch. It is even unclear to me
      how that would be described. There is some code for it left in the
      patch, but 'an_master' is always passed as false.
      Signed-off-by: default avatarVladimir Oltean <vladimir.oltean@nxp.com>
      Reviewed-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      ffe10e67