- 07 Jan, 2020 7 commits
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Evan Quan authored
Support custom power profile mode settings on Arcturus. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Xiaojie Yuan authored
kernel_fpu_begin/_end() are already called inside dcn20_resource_construct, and calling kernel_fpu_begin/_end() recursively triggers WARN_ON() when CONFIG_X86_DEBUG_FPU is enabled. [ 107.060434] WARNING: CPU: 6 PID: 1370 at arch/x86/kernel/fpu/core.c:90 kernel_fpu_begin+0xbd/0xe0 <snip> [ 107.268197] Call Trace: [ 107.270751] dcn20_patch_bounding_box+0x17/0x100 [amdgpu] [ 107.276204] init_soc_bounding_box+0x1b3/0x5f0 [amdgpu] [ 107.281536] ? _cond_resched+0x19/0x30 [ 107.285307] dcn20_resource_construct+0x3a9/0xa90 [amdgpu] [ 107.290957] ? dcn20_resource_construct+0x3a9/0xa90 [amdgpu] [ 107.296621] ? __alloc_pages_nodemask+0x16a/0x330 [ 107.301476] ? _cond_resched+0x19/0x30 [ 107.305284] ? kmem_cache_alloc_trace+0x197/0x230 [ 107.310063] ? _cond_resched+0x19/0x30 [ 107.313783] ? kmem_cache_alloc_trace+0x197/0x230 [ 107.318691] dcn20_create_resource_pool+0x42/0x70 [amdgpu] [ 107.324315] dc_create_resource_pool+0x12d/0x170 [amdgpu] [ 107.329851] dc_create+0x1b8/0x6a0 [amdgpu] [ 107.334013] ? kmem_cache_alloc_trace+0x1e2/0x230 [ 107.338832] amdgpu_dm_init+0x13e/0x1c0 [amdgpu] <snip> Signed-off-by:
Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Felix Kuehling authored
Don't use the HWS if it's known to be hanging. In a reset also don't try to destroy the HIQ because that may hang on SRIOV if the KIQ is unresponsive. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Tested-by:
Emily Deng <Emily.Deng@amd.com> Reviewed-by:
shaoyunl <shaoyun.liu@amd.com> Signed-off-by:
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Felix Kuehling authored
Move HWS hang detection into unmap_queues_cpsch to catch hangs in all cases. If this happens during a reset, don't schedule another reset because the reset already in progress is expected to take care of it. Signed-off-by:
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Felix Kuehling authored
dqm->pipeline_mem wasn't used anywhere. Signed-off-by:
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Felix Kuehling authored
Reading from /sys/kernel/debug/kfd/hang_hws would cause a kernel oops because we didn't implement a read callback. Set the permission to write-only to prevent that. Signed-off-by:
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Chunming Zhou authored
Can expose it now that the khronos has exposed the vlk extension. Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Reviewed-by:
Flora Cui <Flora.Cui@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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- 23 Dec, 2019 32 commits
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zhengbin authored
Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c:674:2-26: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c:794:1-25: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c:897:2-36: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c:1016:1-35: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c:1087:2-34: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c:1177:1-33: WARNING: Assignment of 0/1 to bool variable Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
zhengbin <zhengbin13@huawei.com> Signed-off-by:
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zhengbin authored
Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:132:2-10: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:140:2-10: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:142:13-21: WARNING: Assignment of 0/1 to bool variable Reported-by:
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zhengbin authored
Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:3961:1-19: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:3981:1-19: WARNING: Assignment of 0/1 to bool variable Reported-by:
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zhengbin authored
Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c:255:2-20: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c:267:2-20: WARNING: Assignment of 0/1 to bool variable Reported-by:
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zhengbin authored
Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c:253:2-20: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c:265:2-20: WARNING: Assignment of 0/1 to bool variable Reported-by:
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zhengbin authored
Fixes coccicheck warning: drivers/gpu/drm/radeon/ni.c:2020:2-15: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/radeon/ni.c:2088:2-15: WARNING: Assignment of 0/1 to bool variable Reported-by:
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zhengbin authored
Fixes coccicheck warning: drivers/gpu/drm/radeon/cik.c:8140:2-15: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/radeon/cik.c:8212:2-15: WARNING: Assignment of 0/1 to bool variable Reported-by:
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zhengbin authored
Fixes coccicheck warning: drivers/gpu/drm/radeon/rv770.c:1706:2-15: WARNING: Assignment of 0/1 to bool variable Reported-by:
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zhengbin authored
Fixes coccicheck warning: drivers/gpu/drm/radeon/evergreen.c:4948:2-15: WARNING: Assignment of 0/1 to bool variable Reported-by:
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zhengbin authored
Fixes coccicheck warning: drivers/gpu/drm/radeon/r600.c:3056:2-15: WARNING: Assignment of 0/1 to bool variable Reported-by:
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zhengbin authored
Fixes coccicheck warning: drivers/gpu/drm/radeon/si.c:6475:2-15: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/radeon/si.c:6542:2-15: WARNING: Assignment of 0/1 to bool variable Reported-by:
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zhengbin authored
Fixes coccicheck warning: drivers/gpu/drm/radeon/r100.c:1826:3-31: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/radeon/r100.c:1828:3-31: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/radeon/r100.c:2390:2-22: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/radeon/r100.c:2395:2-22: WARNING: Assignment of 0/1 to bool variable Reported-by:
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Alex Deucher authored
Add defined peak sclk for navi12 peak profile mode. Reviewed-by:
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Alex Deucher authored
Fetch the sclk from the pptable if there is no specified sclk for the board. Reviewed-by:
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Guchun Chen authored
Return value should be set when going to error handle tag for error case, this can avoid potential invalid array access by upper caller. Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Frank.Min authored
FB location is already programmed by HV driver for arcutus so remove this part Signed-off-by:
Frank.Min <Frank.Min@amd.com> Reviewed-by:
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Frank.Min authored
1. enable xgmi ta initialization for sriov 2. enable xgmi initialization for sriov Signed-off-by:
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Tianci.Yin authored
IP discovery TMR(occupied the top VRAM with size DISCOVERY_TMR_SIZE) has been reserved, and the p2c buffer is in the range of this TMR, so the p2c buffer reservation is unnecessary. Reviewed-by:
Kevin Wang <kevin1.wang@amd.com> Reviewed-by:
Tianci.Yin <tianci.yin@amd.com> Signed-off-by:
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Tianci.Yin authored
The method of getting fb_loc changed from parsing VBIOS to taking certain offset from top of VRAM Reviewed-by:
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Ma Feng authored
Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/navi10_ih.c:113:5-8: Unneeded variable: "ret". Return "0" on line 182 Reported-by:
Ma Feng <mafeng.ma@huawei.com> Signed-off-by:
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Ma Feng authored
Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1036:5-8: Unneeded variable: "ret". Return "0" on line 1079 Reported-by:
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James Zhu authored
Add mmSDMA2-7_EDC_COUNTER to support Arcturus Signed-off-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
Yong Zhao <Yong.Zhao@amd.com> Signed-off-by:
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James Zhu authored
Add mmCOMPUTE_STATIC_THREAD_MGMT_SE4-7 to support Arcturus Signed-off-by:
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James Zhu authored
Replace ARRAY_SIZE with size variables to support different ASICs. Signed-off-by:
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James Zhu authored
Arcturus has 8 SEs. Add mmCOMPUTE_STATIC_THREAD_MGMT_SE4-7 for EDC GPR _workarounds, Signed-off-by:
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John Clements authored
Devices newer then VEGA10/12 shall have these programming sequences performed by PSP BL Reviewed-by:
John Clements <john.clements@amd.com> Signed-off-by:
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Frank.Min authored
max range of the agp aperture is 48 bits, so enlarge agp_start address into 48bit with all bits set Signed-off-by:
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Jane Jian authored
currently using TMR loading VCN fw MMSCH would fail to init after FLR, just disable ib test for temporarily daily testing, continuing debug with mm team. Signed-off-by:
Jane Jian <Jane.Jian@amd.com> Acked-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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Le Ma authored
This workaround does not affect other asics because amdgpu only need expose one gfx sched to user for now. Signed-off-by:
Le Ma <le.ma@amd.com> Reviewed-by:
Nirmoy Das <nirmoy.das@amd.com> Signed-off-by:
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Jonathan Kim authored
The DF routines to arm xGMI performance will attempt to re-arm both on performance monitoring start and read on initial failure to arm. Signed-off-by:
Jonathan Kim <Jonathan.Kim@amd.com> Reviewed-by:
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Jonathan Kim authored
During DF C-State, Perfmon counters outside of range 1D700-1D7FF will encounter SLVERR affecting xGMI performance monitoring. PerfmonCtr[7:4] is being added to avoid SLVERR during read since it falls within this range. PerfmonCtl[7:4] is being added in order to arm PerfmonCtr[7:4]. Since PerfmonCtl[7:4] exists outside of range 1D700-1D7FF, DF routines will be enabled to opportunistically re-arm PerfmonCtl[7:4] on retry after SLVERR. Signed-off-by:
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Luben Tuikov authored
Simplify padding calculations. v2: Comment update and spacing. Signed-off-by:
Luben Tuikov <luben.tuikov@amd.com> Reviewed-by:
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- 19 Dec, 2019 1 commit
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Huang Rui authored
Thunk driver would like to know the num_cp_queues data, however this data relied on different asic specific. So it's better to get it from kfd driver. v2: don't update name size. Signed-off-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
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