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- 17 Jan, 2012 3 commits
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Adam Jackson authored
This is paranoid, but I am entirely willing to believe the hardware could come up with a condition where I get a status with both the 'done' and 'receive error' bits set. Signed-off-by:
Adam Jackson <ajax@redhat.com> Acked-by:
Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Adam Jackson authored
The default in the Sandybridge docs is 5, as on Ironlake, and I have no reason to believe 3 would work any better. Signed-off-by:
Adam Jackson <ajax@redhat.com> Acked-by:
Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Adam Jackson authored
Matches the advice in the Sandybridge documentation. Signed-off-by:
Adam Jackson <ajax@redhat.com> Acked-by:
Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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- 20 Dec, 2011 1 commit
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Wu Fengguang authored
On DP monitor hot remove, clear DP_AUDIO_OUTPUT_ENABLE accordingly, so that the audio driver will receive hot plug events and take action to refresh its device state and ELD contents. Note that the DP_AUDIO_OUTPUT_ENABLE bit may be enabled or disabled only when the link training is complete and set to "Normal". Tested OK for both hot plug/remove and DPMS on/off. Signed-off-by:
Wu Fengguang <fengguang.wu@intel.com> Signed-off-by:
Keith Packard <keithp@keithp.com>
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- 16 Dec, 2011 1 commit
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Adam Jackson authored
Some active adaptors (VGA usually) only have two lanes at 2.7GHz. That's a maximum pixel clock of 144MHz at 8bpc, but 192MHz at 6bpc. Fixes Asus UX31 panel being black at startup due to no valid modes since dc22ee6f. v2: Rebased to current code, resulting in the fix applying to EDP panels as well. Also changed from spatio-temporal to just spatial dithering on pre-ironlake, to be conssitent (and less visual flicker) Signed-off-by:
Adam Jackson <ajax@redhat.com> Signed-off-by:
Eric Anholt <eric@anholt.net> Tested-by:
Eric Anholt <eric@anholt.net> Tested-by:
Dirk Hohndel <hohndel@infradead.org> Signed-off-by:
Keith Packard <keithp@keithp.com>
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- 23 Nov, 2011 1 commit
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Keith Packard authored
The Ivybridge eDP control register looks like a cross between a Cougarpoint PCH DP control register and a Sandybridge eDP control register. Where things trivially match, share the code. Where there are any tricky bits, just split things out into two obviously separate code paths. Signed-off-by:
Keith Packard <keithp@keithp.com> Tested-by:
Fang Xun <xunx.fang@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41991
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- 17 Nov, 2011 9 commits
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Keith Packard authored
The BIOS VBT value for an eDP panel has been shown to be incorrect on one machine, and we haven't found any machines where the DPCD value was wrong, so we'll use the DPCD value everywhere. Signed-off-by:
Keith Packard <keithp@keithp.com> Reviewed-by:
Adam Jackson <ajax@redhat.com> Reviewed-by:
Jesse Barnes <jbarnes@virtuousgeek.org>
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Keith Packard authored
Limit the link training setting command to the lanes needed for the current mode. It seems vaguely possible that a monitor will try to train the other lanes and fail in some way, so this seems like the safer plan. Signed-off-by:
Keith Packard <keithp@keithp.com> Reviewed-by:
Jesse Barnes <jbarnes@virtuousgeek.org>
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Keith Packard authored
Found a couple of bare tabs in intel_dp.c Signed-off-by:
Keith Packard <keithp@keithp.com> Reviewed-by:
Jesse Barnes <jbarnes@virtuousgeek.org>
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Keith Packard authored
Instead of going through the sequence just once, run through the whole set up to 5 times to see if something can work. This isn't part of the DP spec, but the BIOS seems to do it, and given that link training failure is so bad, it seems reasonable to follow suit. Signed-off-by:
Keith Packard <keithp@keithp.com> Reviewed-by:
Jesse Barnes <jbarnes@virtuousgeek.org>
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Keith Packard authored
Make sure the sequence of operations in all three functions makes sense: 1) The backlight must be off unless the screen is running 2) The link must be running to turn the eDP panel on/off 3) The CPU eDP PLL must be running until everything is off Signed-off-by:
Keith Packard <keithp@keithp.com>
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Keith Packard authored
The panel power sequencing hardware tracks the stages of panel power sequencing and signals when the panel is completely on or off. Instead of blindly assuming the panel timings will work, poll the panel power status register until it shows the correct values. Signed-off-by:
Keith Packard <keithp@keithp.com> Reviewed-by:
Jesse Barnes <jbarnes@virtuousgeek.org>
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Keith Packard authored
PCH eDP has many of the same needs as regular PCH DP connections, including the DP_CTl bit settings, the TRANS_DP_CTL register. Signed-off-by:
Keith Packard <keithp@keithp.com> Reviewed-by:
Jesse Barnes <jbarnes@virtuousgeek.org>
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Keith Packard authored
No persistent data was ever stored here, so link_status is instead allocated on the stack as needed. Signed-off-by:
Keith Packard <keithp@keithp.com> Reviewed-by:
Jesse Barnes <jbarnes@virtuousgeek.org>
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Keith Packard authored
Every usage of PCH_PP_CONTROL sets the PANEL_UNLOCK_REGS value to ensure that writes will be respected, move this to a common function to make the driver cleaner. No functional changes. Signed-off-by:
Keith Packard <keithp@keithp.com>
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- 01 Nov, 2011 1 commit
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Keith Packard authored
Use of the struct_mutex is not correct for locking in mode setting paths. Signed-off-by:
Keith Packard <keithp@keithp.com>
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- 31 Oct, 2011 1 commit
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Paul Gortmaker authored
They need this to get all the EXPORT_SYMBOL variants and THIS_MODULE Signed-off-by:
Paul Gortmaker <paul.gortmaker@windriver.com>
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- 21 Oct, 2011 7 commits
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Adam Jackson authored
According to the gen6 docs, only the DP_A port (on-CPU eDP) still uses the old IBX bit shift for the link training pattern setup bits. Signed-off-by:
Adam Jackson <ajax@redhat.com> Reviewed-by:
Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by:
Keith Packard <keithp@keithp.com>
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Adam Jackson authored
The obvious counterpart to is_pch_edp(). Convert existing instances of the idiom to the new routine. Signed-off-by:
Adam Jackson <ajax@redhat.com> Reviewed-by:
Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by:
Keith Packard <keithp@keithp.com>
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Jesse Barnes authored
DPCD 1.1+ adds some automated test infrastructure support. Add support for reading the IRQ source and jumping to a test handling routine if needed. Subsequent patches will handle particular tests; this patch just ACKs any requested tests by default. Signed-off-by:
Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by:
Keith Packard <keithp@keithp.com>
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Jesse Barnes authored
Read link status first, followed by the full DPCD receiver cap field rather than just the first 8 bytes. Signed-off-by:
Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by:
Adam Jackson <ajax@redhat.com> Signed-off-by:
Keith Packard <keithp@keithp.com>
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Adam Jackson authored
These were just working around the math being wrong. Signed-off-by:
Adam Jackson <ajax@redhat.com> Signed-off-by:
Keith Packard <keithp@keithp.com>
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Adam Jackson authored
The previous code was confused about units, which is pretty reasonable given that the units themselves are confusing. Signed-off-by:
Adam Jackson <ajax@redhat.com> Signed-off-by:
Keith Packard <keithp@keithp.com>
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Jesse Barnes authored
At the point where we check, we can't do much about the failure, but it can aid debugging. Note that the auto-train override bit will be reset as part of normal mode setting with this patch if a pipe ever does get stuck, but that's consistent with the workaround for CPT provided by the hardware team. This patch helped catch the fact that the pipe wasn't running in the !composite sync FDI case on my IVB SDV, so has already shown to be useful. Signed-off-by:
Jesse Barnes <jbarnes@virtuousgeek.org> Tested-By:
Eugeni Dodonov <eugeni.dodonov@intel.com> Reviewed-By:
Eugeni Dodonov <eugeni.dodonov@intel.com> Signed-off-by:
Keith Packard <keithp@keithp.com>
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- 20 Oct, 2011 1 commit
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Jesse Barnes authored
Well almost anyway. IVB has 3 planes, pipes, transcoders, and FDI interfaces, but only 2 pipe PLLs. So two of the pipes must use the same pipe timings (e.g. 2 DP plus one other, or two HDMI with the same mode and one other, etc.). Signed-off-by:
Jesse Barnes <jbarnes@virtuousgeek.org> Tested-By:
Eugeni Dodonov <eugeni.dodonov@intel.com> Reviewed-By:
Eugeni Dodonov <eugeni.dodonov@intel.com> Signed-off-by:
Keith Packard <keithp@keithp.com>
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- 12 Oct, 2011 2 commits
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Keith Packard authored
If the panel is powered up, there's no need to delay for the 'off' interval when turning the panel on. Signed-off-by:
Keith Packard <keithp@keithp.com>
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Keith Packard authored
This eliminates a fairly long delay when power sequencing newer hardware Signed-off-by:
Keith Packard <keithp@keithp.com> Reviewed-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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- 06 Oct, 2011 10 commits
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Keith Packard authored
There's no good reason to turn off the eDP force VDD bit synchronously while probing devices; that just sticks a huge delay into all mode setting paths. Instead, queue a delayed work proc to disable the VDD force bit and then remember when that fires to ensure that the appropriate delay is respected before trying to turn it back on. Signed-off-by:
Keith Packard <keithp@keithp.com>
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Keith Packard authored
We need to check eDP VDD force and panel on in several places, so create some simple helper functions to avoid duplicating code. Signed-off-by:
Keith Packard <keithp@keithp.com>
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Keith Packard authored
The return value was unused, so just stop doing that. Signed-off-by:
Keith Packard <keithp@keithp.com> Reviewed-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Keith Packard authored
This value doesn't come directly from the VBT, and so is rather specific to the particular DP output. Signed-off-by:
Keith Packard <keithp@keithp.com> Reviewed-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Keith Packard authored
Store the panel power sequencing delays in the dp private structure, rather than the global device structure. Who knows, maybe we'll get more than one eDP device in the future. From the eDP spec, we need the following numbers: T1 + T3 Power on to Aux Channel operation (panel_power_up_delay) This marks how long it takes the panel to boot up and get ready to receive aux channel communications. T8 Video signal to backlight on (backlight_on_delay) Once a valid video signal is being sent to the device, it can take a while before the panel is actuall showing useful data. This delay allows the panel to get something reasonable up before the backlight is turned on. T9 Backlight off to video off (backlight_off_delay) Turning the backlight off can take a moment, so this delay makes sure there is still valid video data on the screen. T10 Video off to power off (panel_power_down_delay) Presumably this delay allows the panel to perform an orderly shutdown of the display. T11 + T12 Power off to power on (panel_power_cycle_delay) So, once you turn the panel off, you have to wait a while before you can turn it back on. This delay is usually the longest in the entire sequence. Neither the VBIOS source code nor the hardware documentation has a clear mapping between the delay values they provide and those required by the eDP spec. The VBIOS code actually uses two different labels for the delay values in the five words of the relevant VBT table. **** MORE LATER *** Look at both the current hardware register settings and the VBT specified panel power sequencing timings. Use the maximum of the two delays, to make sure things work reliably. If there is no VBT data, then those values will be initialized to zero, so we'll just use the values as programmed in the hardware. Note that the BIOS just fetches delays from the VBT table to place in the hardware registers, so we should get the same values from both places, except for rounding. VBT doesn't provide any values for T1 or T2, so we'll always just use the hardware value for that. The panel power up delay is thus T1 + T2 + T3, which should be sufficient in all cases. The panel power down delay is T1 + T2 + T12, using T1+T2 as a proxy for T11, which isn't available anywhere. For the backlight delays, the eDP spec says T6 + T8 is the delay from the end of link training to backlight on and T9 is the delay from backlight off until video off. The hardware provides a 'backlight on' delay, which I'm taking to be T6 + T8 while the VBT provides something called 'T7', which I'm assuming is s On the macbook air I'm testing with, this yields a power-up delay of over 200ms and a power-down delay of over 600ms. It all works now, but we're frobbing these power controls several times during mode setting, making the whole process take an awfully long time. Signed-off-by:
Keith Packard <keithp@keithp.com>
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Keith Packard authored
Any call to intel_dp_sink_dpms must ensure that the panel has power so that the DP_SET_POWER operation will be correctly received. The only one missing this was in intel_dp_prepare. Signed-off-by:
Keith Packard <keithp@keithp.com> Reviewed-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Keith Packard authored
The DP i2c initialization code does a couple of i2c transactions, which means that an eDP panel must be powered up. Signed-off-by:
Keith Packard <keithp@keithp.com> Reviewed-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Keith Packard authored
Talking to the eDP DDC channel requires that the panel be powered up. Wrap both the EDID and modes fetch code with calls to turn the vdd power on and back off. Signed-off-by:
Keith Packard <keithp@keithp.com> Reviewed-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Keith Packard authored
On eDP, DDC requires panel power, but turning that on uses the panel power sequencing timing values fetch from the DPCD data. Signed-off-by:
Keith Packard <keithp@keithp.com> Reviewed-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Keith Packard authored
If the panel is already off, we'll need to turn VDD on to execute the (useless) DPMS off code. Yes, it would be better to just not do any of this, but correctness, and *then* performance. Signed-off-by:
Keith Packard <keithp@keithp.com>
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- 30 Sep, 2011 3 commits
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Keith Packard authored
The VDD force bit is turned on before touching the panel, but if it was enabled, there was no call to turn it back off. Add a call. Signed-off-by:
Keith Packard <keithp@keithp.com> Reviewed-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Keith Packard authored
Cleans up code dealing with eDP a bit. Remove redundant checks in callers Signed-off-by:
Keith Packard <keithp@keithp.com>
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Keith Packard authored
Avoid any question about locked registers by just writing the unlock pattern with every write to the register. Signed-off-by:
Keith Packard <keithp@keithp.com>
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