- 15 Oct, 2019 39 commits
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Alex Deucher authored
This adds BACO support for Polaris asics. Reviewed-by:
Evan Quan <evan.quan@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
This adds BACO support for Iceland asics. Reviewed-by:
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Alex Deucher authored
This adds BACO support for Tonga. Reviewed-by:
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Alex Deucher authored
This adds core support for BACO on pre-vega asics. Reviewed-by:
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
Add support for vega20 when the swSMU path is used. Reviewed-by:
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Alex Deucher authored
It was a vega20 specific hack. Check if we are in reset and what reset method we are using. Reviewed-by:
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Alex Deucher authored
Use the base class rather than the specific class and drop the second loop. Reviewed-by:
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Alex Deucher authored
Move it into the caller. There are cases were we don't want it. We need it for hibernation, but we don't need it for runtime pm, so drop it for runtime pm. Reviewed-by:
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Alex Deucher authored
for amdgpu_device_suspend. This follows the logic in the resume path. Reviewed-by:
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Alex Deucher authored
This reverts commit 6f7fe9a9. This breaks some boards. Maybe just enable this on PPC for now? Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205147Signed-off-by:
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Hersen Wu authored
when CONFIG_DRM_AMD_DC_DCN2_1 is not enable in .config, there is build error. struct dpm_clocks shoud not be guarded. Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Reviewed-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
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Hersen Wu authored
enable dc get dmp clock table and set dcn watermarks via pplib. Signed-off-by:
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Andrey Grodzovsky authored
Ignre the ERREVENT_ATHUB_INTERRUPT for systems without RAS. Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-and-tested-by:
Jack Zhang <Jack.Zhang1@amd.com> Acked-by:
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Philip Yang authored
user_pages array should always be freed after validation regardless if user pages are changed after bo is created because with HMM change parse bo always allocate user pages array to get user pages for userptr bo. v2: remove unused local variable and amend commit v3: add back get user pages in gem_userptr_ioctl, to detect application bug where an userptr VMA is not ananymous memory and reject it. Bugzilla: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1844962Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Tested-by:
Joe Barnett <thejoe@gmail.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Hersen Wu authored
there are two paths for renoir dc access smu. one dc access smu directly using bios smc interface: set disply, dprefclk, etc. another goes through pplib for get dpm clock table and set watermmark. Signed-off-by:
Kevin Wang <kevin1.wang@amd.com> Signed-off-by:
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Evan Quan authored
Enable runtime VCN DPM on/off on Arcturus. Signed-off-by:
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Kenneth Feng authored
Bug fix for pcie paramerers override on swsmu. Below is a scenario to have this problem. pptable definition on pcie dpm: 0 -> pcie gen speed:1, pcie lanes: *16 1 -> pcie gen speed:4, pcie lanes: *16 Then if we have a system only have the capbility: pcie gen speed: 3, pcie lanes: *8, we will override dpm 1 to pcie gen speed 3, pcie lanes *8. But the code skips the dpm 0 configuration. So the real pcie dpm parameters are: 0 -> pcie gen speed:1, pcie lanes: *16 1 -> pcie gen speed:3, pcie lanes: *8 Then the wrong pcie lanes will be toggled. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
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Emily Deng authored
When index is 1, need to set compute ring timeout for sriov and passthrough. Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Reviewed-by:
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Christian König authored
When we allocate new page tables under memory pressure we should not evict old ones. Signed-off-by:
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Christian König authored
We need to drop normal and userptr BOs separately. Signed-off-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Dennis Li authored
v1: Add codes to query the EDC count of VML2 & ATCL2 v2: Rename VML2/ATCL2 registers and drop their mask define v3: Add back the ECC mask for VML2 registers Signed-off-by:
Dennis Li <Dennis.Li@amd.com> Reviewed-by:
Hawking Zhang <hawking.zhang@amd.com> Acked-by:
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Dennis Li authored
Add VML2 and ATCL2 ECC registers to support VEGA20 RAS Signed-off-by:
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Dennis Li authored
For the potential request in the future, change to query the actual EDC counter. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Le Ma authored
BACO reset is needed for RAS recovery. Signed-off-by:
Le Ma <le.ma@amd.com> Reviewed-by:
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Le Ma authored
1 indicates RAS recovery flag in SMU FW. Signed-off-by:
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Le Ma authored
Program THM_BACO_CNTL.SOC_DOMAIN_IDLE=1 will tell VBIOS to disable ECC when BACO exit. This can save BACO exit time by PSP on none-ECC SKU. Drop the setting for ECC supported SKU. Signed-off-by:
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Le Ma authored
Workaround to make RAS recovery work in BACO reset. Signed-off-by:
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Hans de Goede authored
Bail from the pci_driver probe function instead of from the drm_driver load function. This avoid /dev/dri/card0 temporarily getting registered and then unregistered again, sending unwanted add / remove udev events to userspace. Specifically this avoids triggering the (userspace) bug fixed by this plymouth merge-request: https://gitlab.freedesktop.org/plymouth/plymouth/merge_requests/59 Note that despite that being a userspace bug, not sending unnecessary udev events is a good idea in general. BugLink: https://bugzilla.redhat.com/show_bug.cgi?id=1490490Reviewed-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
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Alex Deucher authored
Use the dcn21 functions in dcn21_resource.c and make the dcn20 functions static since they are only used in dcn20_resource now. Cc: bhawanpreet.lakha@amd.com Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Xiaojie Yuan authored
SMU firmware has fix the bug, so remove this workaround. Signed-off-by:
Xiaojie Yuan <xiaojie.yuan@amd.com> Acked-by:
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Xiaojie Yuan authored
IP Discovery data is TMR fenced by the latest PSP BL, so we need to reserve this region. Tested on navi10/12/14 with VBIOS integrated with latest PSP BL. v2: use DISCOVERY_TMR_SIZE macro as bo size use amdgpu_bo_create_kernel_at() to allocate bo Signed-off-by: -
Kevin Wang authored
add navi14 umd pstate peak clock support. NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK 1670 MHz NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK 1448 MHz NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK 1181 MHz NAVI14_UMD_PSTATE_PEAK_XTX_GFXCLK 1717 MHz NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK 1448 MHz Signed-off-by:
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Evan Quan authored
Currently this is only supported on Vega20 with 40.50 and later SMC firmware. Signed-off-by:
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Evan Quan authored
Currently this is only supported on Vega20 with 40.50 and later SMC firmware. Signed-off-by:
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- 11 Oct, 2019 1 commit
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Alex Deucher authored
Add toggles for more power features. Helpful in debugging. Reviewed-by:
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