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  1. 16 Jul, 2010 1 commit
  3. 06 Jul, 2010 12 commits
    • Chris Metcalf's avatar
      Merge branch 'master' into for-linus · a2262d8a
      Chris Metcalf authored
      a2262d8a
    • Chris Metcalf's avatar
      arch/tile: catch up on various minor cleanups. · ef06f55a
      Chris Metcalf authored 
      None of these changes fix any actual bugs, but are just various cleanups
that fell out along the way.  In particular, some unused #defines and
includes are removed, PREFETCH_STRIDE is added (the default is right for
our shipping chips, but wrong for our next generation), our tile-specific
prefetching code is removed so the (identical) generic prefetching code
can be used instead, a comment is fixed to be proper GPL and not just a
"paste GPL here" token, a "//" comment is converted to "/* */", etc.
Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
      ef06f55a
    • Chris Metcalf's avatar
      arch/tile: avoid erroneous error return for PTRACE_POKEUSR. · bcd97c3f
      Chris Metcalf authored 
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
      bcd97c3f
    • FUJITA Tomonori's avatar
      tile: set ARCH_KMALLOC_MINALIGN · c6673cb5
      FUJITA Tomonori authored 
      Architectures that handle DMA-non-coherent memory need to set
ARCH_KMALLOC_MINALIGN to make sure that kmalloc'ed buffer is DMA-safe:
the buffer doesn't share a cache with the others.
Signed-off-by: default avatarFUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp>
Acked-by: default avatarChris Metcalf <cmetcalf@tilera.com>
      c6673cb5
    • FUJITA Tomonori's avatar
      tile: remove homegrown L1_CACHE_ALIGN macro · 4b2bf4b3
      FUJITA Tomonori authored 
      Let's use the standard L1_CACHE_ALIGN macro instead.
Signed-off-by: default avatarFUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp>
Acked-by: default avatarChris Metcalf <cmetcalf@tilera.com>
      4b2bf4b3
    • Chris Metcalf's avatar
      arch/tile: Miscellaneous cleanup changes. · 0707ad30
      Chris Metcalf authored 
      This commit is primarily changes caused by reviewing "sparse"
and "checkpatch" output on our sources, so is somewhat noisy, since
things like "printk() -> pr_err()" (or whatever) throughout the
codebase tend to get tedious to read.  Rather than trying to tease
apart precisely which things changed due to which type of code
review, this commit includes various cleanups in the code:

- sparse: Add declarations in headers for globals.
- sparse: Fix __user annotations.
- sparse: Using gfp_t consistently instead of int.
- sparse: removing functions not actually used.
- checkpatch: Clean up printk() warnings by using pr_info(), etc.;
  also avoid partial-line printks except in bootup code.
  - checkpatch: Use exposed structs rather than typedefs.
  - checkpatch: Change some C99 comments to C89 comments.

In addition, a couple of minor other changes are rolled in
to this commit:

- Add support for a "raise" instruction to cause SIGFPE, etc., to be raised.
- Remove some compat code that is unnecessary when we fully eliminate
  some of the deprecated syscalls from the generic syscall ABI.
- Update the tile_defconfig to reflect current config contents.
Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
      0707ad30
    • Chris Metcalf's avatar
      arch/tile: Split the icache flush code off to a generic <arch> header. · c78095bd
      Chris Metcalf authored 
      This code is used in other places in our system than in Linux, so
to share it we now implement it as an inline function in our low-level
<arch> headers, and instantiate it in one file in Linux's arch/tile/lib.
The file is now cacheflush.c and is C code rather than the strangely-named
and assembler-implemented __invalidate_icache.S.
Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
      c78095bd
    • Chris Metcalf's avatar
      arch/tile: Fix bug in support for atomic64_xx() ops. · 2db09827
      Chris Metcalf authored 
      This wasn't properly tested until the perf-event subsystem started
to get brought up under the tile architecture.

The bug caused bogus atomic64_cmpxchg() values to be returned,
among other things.
Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
      2db09827
    • Chris Metcalf's avatar
      arch/tile: Shrink the tile-opcode files considerably. · 863fbac6
      Chris Metcalf authored 
      The C file (tile-desc_{32,64}.c) was about 300KB before this change,
and is now shrunk down to 100K.  The original file included support
for BFD in the binutils toolchain, which is not necessary in the
kernel; the kernel version only needs to include enough support to
enable the single-stepper and backtracer.
Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
      863fbac6
    • Chris Metcalf's avatar
      arch/tile: Add driver to enable access to the user dynamic network. · 9f9c0382
      Chris Metcalf authored 
      This network (the "UDN") connects all the cpus on the chip in a
wormhole-routed dynamic network.  Subrectangles of the chip can
be allocated by a "create" ioctl on /dev/hardwall, and then to access the
UDN in that rectangle, tasks must perform an "activate" ioctl on that
same file object after affinitizing themselves to a single cpu in
the region.  Sending a wormhole-routed message that tries to leave
that subrectangle causes all activated tasks to receive a SIGILL
(just as they would if they tried to access the UDN without first
activating themselves to a hardwall rectangle).

The original submission of this code to LKML had the driver
instantiated under /proc/tile/hardwall.  Now we just use a character
device for this, conventionally /dev/hardwall.  Some futures planning
for the TILE-Gx chip suggests that we may want to have other types of
devices that share the general model of "bind a task to a cpu, then
'activate' a file descriptor on a pseudo-device that gives access to
some hardware resource".  As such, we are using a device rather
than, for example, a syscall, to set up and activate this code.

As part of this change, the compat_ptr() declaration was fixed and used
to pass the compat_ioctl argument to the normal ioctl.  So far we limit
compat code to 2GB, so the difference between zero-extend and sign-extend
(the latter being correct, eventually) had been overlooked.
Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
      9f9c0382
    • Chris Metcalf's avatar
      arch/tile: Enable more sophisticated IRQ model for 32-bit chips. · fb702b94
      Chris Metcalf authored 
      This model is based on the on-chip interrupt model used by the
TILE-Gx next-generation hardware, and interacts much more cleanly
with the Linux generic IRQ layer.

The change includes modifications to the Tilera hypervisor, which
are reflected in the hypervisor headers in arch/tile/include/arch/.
Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
Acked-by: default avatarThomas Gleixner <tglx@linutronix.de>
      fb702b94
    • Chris Metcalf's avatar
      Move list types from <linux/list.h> to <linux/types.h>. · de5d9bf6
      Chris Metcalf authored 
      This allows a list_head (or hlist_head, etc.) to be used from places
that used to be impractical, in particular <asm/processor.h>, which
used to cause include file recursion: <linux/list.h> includes
<linux/prefetch.h>, which always includes <asm/processor.h> for the
prefetch macros, as well as <asm/system.h>, which often includes
<asm/processor.h> directly or indirectly.

This avoids a lot of painful workaround hackery on the tile
architecture, where we use a list_head in the thread_struct to chain
together tasks that are activated on a particular hardwall.
Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
Reviewed-by: default avatarMatthew Wilcox <willy@linux.intel.com>
      de5d9bf6
  5. 05 Jul, 2010 8 commits
  7. 04 Jul, 2010 1 commit
    • Will Deacon's avatar
      ARM: 6205/1: perf: ensure counter delta is treated as unsigned · 446a5a8b
      Will Deacon authored 
      Hardware performance counters on ARM are 32-bits wide but atomic64_t
variables are used to represent counter data in the hw_perf_event structure.

The armpmu_event_update function right-shifts a signed 64-bit delta variable
and adds the result to the event count. This can lead to shifting in sign-bits
if the MSB of the 32-bit counter value is set. This results in perf output
such as:

 Performance counter stats for 'sleep 20':

 18446744073460670464  cycles             <-- 0xFFFFFFFFF12A6000
        7783773  instructions             #      0.000 IPC
            465  context-switches
            161  page-faults
        1172393  branches

   20.154242147  seconds time elapsed

This patch ensures that the delta value is treated as unsigned so that the
right shift sets the upper bits to zero.

Cc: <stable@kernel.org>
Acked-by: default avatarJamie Iles <jamie.iles@picochip.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      446a5a8b
  9. 03 Jul, 2010 1 commit
  11. 02 Jul, 2010 15 commits
  13. 01 Jul, 2010 2 commits
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