1. 31 Mar, 2015 1 commit
  2. 30 Mar, 2015 8 commits
  3. 27 Mar, 2015 31 commits
    • James Hogan's avatar
      MIPS: KVM: Wire up MSA capability · d952bd07
      James Hogan authored
      Now that the code is in place for KVM to support MIPS SIMD Architecutre
      (MSA) in MIPS guests, wire up the new KVM_CAP_MIPS_MSA capability.
      
      For backwards compatibility, the capability must be explicitly enabled
      in order to detect or make use of MSA from the guest.
      
      The capability is not supported if the hardware supports MSA vector
      partitioning, since the extra support cannot be tested yet and it
      extends the state that the userland program would have to save.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Acked-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: Jonathan Corbet <corbet@lwn.net>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Cc: linux-api@vger.kernel.org
      Cc: linux-doc@vger.kernel.org
      d952bd07
    • James Hogan's avatar
      MIPS: KVM: Expose MSA registers · ab86bd60
      James Hogan authored
      Add KVM register numbers for the MIPS SIMD Architecture (MSA) registers,
      and implement access to them with the KVM_GET_ONE_REG / KVM_SET_ONE_REG
      ioctls when the MSA capability is enabled (exposed in a later patch) and
      present in the guest according to its Config3.MSAP bit.
      
      The MSA vector registers use the same register numbers as the FPU
      registers except with a different size (128bits). Since MSA depends on
      Status.FR=1, these registers are inaccessible when Status.FR=0. These
      registers are returned as a single native endian 128bit value, rather
      than least significant half first with each 64-bit half native endian as
      the kernel uses internally.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Paul Burton <paul.burton@imgtec.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: Jonathan Corbet <corbet@lwn.net>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Cc: linux-api@vger.kernel.org
      Cc: linux-doc@vger.kernel.org
      ab86bd60
    • James Hogan's avatar
      MIPS: KVM: Add MSA exception handling · c2537ed9
      James Hogan authored
      Add guest exception handling for MIPS SIMD Architecture (MSA) floating
      point exceptions and MSA disabled exceptions.
      
      MSA floating point exceptions from the guest need passing to the guest
      kernel, so for these a guest MSAFPE is emulated.
      
      MSA disabled exceptions are normally handled by passing a reserved
      instruction exception to the guest (because no guest MSA was supported),
      but the hypervisor can now handle them if the guest has MSA by passing
      an MSA disabled exception to the guest, or if the guest has MSA enabled
      by transparently restoring the guest MSA context and enabling MSA and
      the FPU.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Paul Burton <paul.burton@imgtec.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      c2537ed9
    • James Hogan's avatar
      MIPS: KVM: Emulate MSA bits in COP0 interface · 2b6009d6
      James Hogan authored
      Emulate MSA related parts of COP0 interface so that the guest will be
      able to enable/disable MSA (Config5.MSAEn) once the MSA capability has
      been wired up.
      
      As with the FPU (Status.CU1) setting Config5.MSAEn has no immediate
      effect if the MSA state isn't live, as MSA state is restored lazily on
      first use. Changes after the MSA state has been restored take immediate
      effect, so that the guest can start getting MSA disabled exceptions
      right away for guest MSA operations. The MSA state is saved lazily too,
      as MSA may get re-enabled in the near future anyway.
      
      A special case is also added for when Status.CU1 is set while FR=0 and
      the MSA state is live. In this case we are at risk of getting reserved
      instruction exceptions if we try and save the MSA state, so we lose the
      MSA state sooner while MSA is still usable.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Paul Burton <paul.burton@imgtec.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      2b6009d6
    • James Hogan's avatar
      MIPS: KVM: Add base guest MSA support · 539cb89f
      James Hogan authored
      Add base code for supporting the MIPS SIMD Architecture (MSA) in MIPS
      KVM guests. MSA cannot yet be enabled in the guest, we're just laying
      the groundwork.
      
      As with the FPU, whether the guest's MSA context is loaded is stored in
      another bit in the fpu_inuse vcpu member. This allows MSA to be disabled
      when the guest disables it, but keeping the MSA context loaded so it
      doesn't have to be reloaded if the guest re-enables it.
      
      New assembly code is added for saving and restoring the MSA context,
      restoring only the upper half of the MSA context (for if the FPU context
      is already loaded) and for saving/clearing and restoring MSACSR (which
      can itself cause an MSA FP exception depending on the value). The MSACSR
      is restored before returning to the guest if MSA is already enabled, and
      the existing FP exception die notifier is extended to catch the possible
      MSA FP exception and step over the ctcmsa instruction.
      
      The helper function kvm_own_msa() is added to enable MSA and restore
      the MSA context if it isn't already loaded, which will be used in a
      later patch when the guest attempts to use MSA for the first time and
      triggers an MSA disabled exception.
      
      The existing FPU helpers are extended to handle MSA. kvm_lose_fpu()
      saves the full MSA context if it is loaded (which includes the FPU
      context) and both kvm_lose_fpu() and kvm_drop_fpu() disable MSA.
      
      kvm_own_fpu() also needs to lose any MSA context if FR=0, since there
      would be a risk of getting reserved instruction exceptions if CU1 is
      enabled and we later try and save the MSA context. We shouldn't usually
      hit this case since it will be handled when emulating CU1 changes,
      however there's nothing to stop the guest modifying the Status register
      directly via the comm page, which will cause this case to get hit.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Paul Burton <paul.burton@imgtec.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      539cb89f
    • James Hogan's avatar
      MIPS: KVM: Wire up FPU capability · 5fafd874
      James Hogan authored
      Now that the code is in place for KVM to support FPU in MIPS KVM guests,
      wire up the new KVM_CAP_MIPS_FPU capability.
      
      For backwards compatibility, the capability must be explicitly enabled
      in order to detect or make use of the FPU from the guest.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: Jonathan Corbet <corbet@lwn.net>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Cc: linux-api@vger.kernel.org
      Cc: linux-doc@vger.kernel.org
      5fafd874
    • James Hogan's avatar
      MIPS: KVM: Expose FPU registers · 379245cd
      James Hogan authored
      Add KVM register numbers for the MIPS FPU registers, and implement
      access to them with the KVM_GET_ONE_REG / KVM_SET_ONE_REG ioctls when
      the FPU capability is enabled (exposed in a later patch) and present in
      the guest according to its Config1.FP bit.
      
      The registers are accessible in the current mode of the guest, with each
      sized access showing what the guest would see with an equivalent access,
      and like the architecture they may become UNPREDICTABLE if the FR mode
      is changed. When FR=0, odd doubles are inaccessible as they do not exist
      in that mode.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Acked-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      Cc: Paul Burton <paul.burton@imgtec.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: Jonathan Corbet <corbet@lwn.net>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Cc: linux-api@vger.kernel.org
      Cc: linux-doc@vger.kernel.org
      379245cd
    • James Hogan's avatar
      MIPS: KVM: Add FP exception handling · 1c0cd66a
      James Hogan authored
      Add guest exception handling for floating point exceptions and
      coprocessor 1 unusable exceptions.
      
      Floating point exceptions from the guest need passing to the guest
      kernel, so for these a guest FPE is emulated.
      
      Also, coprocessor 1 unusable exceptions are normally passed straight
      through to the guest (because no guest FPU was supported), but the
      hypervisor can now handle them if the guest has its FPU enabled by
      restoring the guest FPU context and enabling the FPU.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Paul Burton <paul.burton@imgtec.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      1c0cd66a
    • James Hogan's avatar
      MIPS: KVM: Emulate FPU bits in COP0 interface · 6cdc65e3
      James Hogan authored
      Emulate FPU related parts of COP0 interface so that the guest will be
      able to enable/disable the following once the FPU capability has been
      wired up:
      - The FPU (Status.CU1)
      - 64-bit FP register mode (Status.FR)
      - Hybrid FP register mode (Config5.FRE)
      
      Changing Status.CU1 has no immediate effect if the FPU state isn't live,
      as the FPU state is restored lazily on first use. After that, changes
      take place immediately in the host Status.CU1, so that the guest can
      start getting coprocessor unusable exceptions right away for guest FPU
      operations if it is disabled. The FPU state is saved lazily too, as the
      FPU may get re-enabled in the near future anyway.
      
      Any change to Status.FR causes the FPU state to be discarded and FPU
      disabled, as the register state is architecturally UNPREDICTABLE after
      such a change. This should also ensure that the FPU state is fully
      initialised (with stale state, but that's fine) when it is next used in
      the new FP mode.
      
      Any change to the Config5.FRE bit is immediately updated in the host
      state so that the guest can get the relevant exceptions right away for
      single-precision FPU operations.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Paul Burton <paul.burton@imgtec.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      6cdc65e3
    • James Hogan's avatar
      MIPS: KVM: Add base guest FPU support · 98e91b84
      James Hogan authored
      Add base code for supporting FPU in MIPS KVM guests. The FPU cannot yet
      be enabled in the guest, we're just laying the groundwork.
      
      Whether the guest's FPU context is loaded is stored in a bit in the
      fpu_inuse vcpu member. This allows the FPU to be disabled when the guest
      disables it, but keeping the FPU context loaded so it doesn't have to be
      reloaded if the guest re-enables it.
      
      An fpu_enabled vcpu member stores whether userland has enabled the FPU
      capability (which will be wired up in a later patch).
      
      New assembly code is added for saving and restoring the FPU context, and
      for saving/clearing and restoring FCSR (which can itself cause an FP
      exception depending on the value). The FCSR is restored before returning
      to the guest if the FPU is already enabled, and a die notifier is
      registered to catch the possible FP exception and step over the ctc1
      instruction.
      
      The helper function kvm_lose_fpu() is added to save FPU context and
      disable the FPU, which is used when saving hardware state before a
      context switch or KVM exit (the vcpu_get_regs() callback).
      
      The helper function kvm_own_fpu() is added to enable the FPU and restore
      the FPU context if it isn't already loaded, which will be used in a
      later patch when the guest attempts to use the FPU for the first time
      and triggers a co-processor unusable exception.
      
      The helper function kvm_drop_fpu() is added to discard the FPU context
      and disable the FPU, which will be used in a later patch when the FPU
      state will become architecturally UNPREDICTABLE (change of FR mode) to
      force a reload of [stale] context in the new FR mode.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Paul Burton <paul.burton@imgtec.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      98e91b84
    • James Hogan's avatar
      MIPS: KVM: Add vcpu_get_regs/vcpu_set_regs callback · b86ecb37
      James Hogan authored
      Add a vcpu_get_regs() and vcpu_set_regs() callbacks for loading and
      restoring context which may be in hardware registers. This may include
      floating point and MIPS SIMD Architecture (MSA) state which may be
      accessed directly by the guest (but restored lazily by the hypervisor),
      and also dedicated guest registers as provided by the VZ ASE.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      b86ecb37
    • James Hogan's avatar
      MIPS: KVM: Add Config4/5 and writing of Config registers · c771607a
      James Hogan authored
      Add Config4 and Config5 co-processor 0 registers, and add capability to
      write the Config1, Config3, Config4, and Config5 registers using the KVM
      API.
      
      Only supported bits can be written, to minimise the chances of the guest
      being given a configuration from e.g. QEMU that is inconsistent with
      that being emulated, and as such the handling is in trap_emul.c as it
      may need to be different for VZ. Currently the only modification
      permitted is to make Config4 and Config5 exist via the M bits, but other
      bits will be added for FPU and MSA support in future patches.
      
      Care should be taken by userland not to change bits without fully
      handling the possible extra state that may then exist and which the
      guest may begin to use and depend on.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      c771607a
    • James Hogan's avatar
      MIPS: KVM: Simplify default guest Config registers · 2211ee81
      James Hogan authored
      Various semi-used definitions exist in kvm_host.h for the default guest
      config registers. Remove them and use the appropriate values directly
      when initialising the Config registers.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      2211ee81
    • James Hogan's avatar
      MIPS: KVM: Clean up register definitions a little · 7bd4acec
      James Hogan authored
      Clean up KVM_GET_ONE_REG / KVM_SET_ONE_REG register definitions for
      MIPS, to prepare for adding a new group for FPU & MSA vector registers.
      
      Definitions are added for common bits in each group of registers, e.g.
      KVM_REG_MIPS_CP0 = KVM_REG_MIPS | 0x10000, for the coprocessor 0
      registers.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      7bd4acec
    • James Hogan's avatar
      MIPS: KVM: Drop pr_info messages on init/exit · 58a115bc
      James Hogan authored
      The information messages when the KVM module is loaded and unloaded are
      a bit pointless and out of line with other architectures, so lets drop
      them.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      58a115bc
    • James Hogan's avatar
      MIPS: KVM: Sort kvm_mips_get_reg() registers · e93d4c15
      James Hogan authored
      Sort the registers in the kvm_mips_get_reg() switch by register number,
      which puts ERROREPC after the CONFIG registers.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      e93d4c15
    • James Hogan's avatar
      MIPS: KVM: Implement PRid CP0 register access · 1068eaaf
      James Hogan authored
      Implement access to the guest Processor Identification CP0 register
      using the KVM_GET_ONE_REG and KVM_SET_ONE_REG ioctls. This allows the
      owning process to modify and read back the value that is exposed to the
      guest in this register.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      1068eaaf
    • James Hogan's avatar
      MIPS: KVM: Handle TRAP exceptions from guest kernel · 0a560427
      James Hogan authored
      Trap instructions are used by Linux to implement BUG_ON(), however KVM
      doesn't pass trap exceptions on to the guest if they occur in guest
      kernel mode, instead triggering an internal error "Exception Code: 13,
      not yet handled". The guest kernel then doesn't get a chance to print
      the usual BUG message and stack trace.
      
      Implement handling of the trap exception so that it gets passed to the
      guest and the user is left with a more useful log message.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: kvm@vger.kernel.org
      Cc: linux-mips@linux-mips.org
      0a560427
    • James Hogan's avatar
      MIPS: Clear [MSA]FPE CSR.Cause after notify_die() · 64bedffe
      James Hogan authored
      When handling floating point exceptions (FPEs) and MSA FPEs the Cause
      bits of the appropriate control and status register (FCSR for FPEs and
      MSACSR for MSA FPEs) are read and cleared before enabling interrupts,
      presumably so that it doesn't have to go through the pain of restoring
      those bits if the process is pre-empted, since writing those bits would
      cause another immediate exception while still in the kernel.
      
      The bits aren't normally ever restored again, since userland never
      expects to see them set.
      
      However for virtualisation it is necessary for the kernel to be able to
      restore these Cause bits, as the guest may have been interrupted in an
      FP exception handler but before it could read the Cause bits. This can
      be done by registering a die notifier, to get notified of the exception
      when such a value is restored, and if the PC was at the instruction
      which is used to restore the guest state, the handler can step over it
      and continue execution. The Cause bits can then remain set without
      causing further exceptions.
      
      For this to work safely a few changes are made:
      - __build_clear_fpe and __build_clear_msa_fpe no longer clear the Cause
        bits, and now return from exception level with interrupts disabled
        instead of enabled.
      - do_fpe() now clears the Cause bits and enables interrupts after
        notify_die() is called, so that the notifier can chose to return from
        exception without this happening.
      - do_msa_fpe() acts similarly, but now actually makes use of the second
        argument (msacsr) and calls notify_die() with the new DIE_MSAFP,
        allowing die notifiers to be informed of MSA FPEs too.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Acked-by: default avatarRalf Baechle <ralf@linux-mips.org>
      Cc: Paul Burton <paul.burton@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      64bedffe
    • James Hogan's avatar
      MIPS: KVM: Handle MSA Disabled exceptions from guest · 98119ad5
      James Hogan authored
      Guest user mode can generate a guest MSA Disabled exception on an MSA
      capable core by simply trying to execute an MSA instruction. Since this
      exception is unknown to KVM it will be passed on to the guest kernel.
      However guest Linux kernels prior to v3.15 do not set up an exception
      handler for the MSA Disabled exception as they don't support any MSA
      capable cores. This results in a guest OS panic.
      
      Since an older processor ID may be being emulated, and MSA support is
      not advertised to the guest, the correct behaviour is to generate a
      Reserved Instruction exception in the guest kernel so it can send the
      guest process an illegal instruction signal (SIGILL), as would happen
      with a non-MSA-capable core.
      
      Fix this as minimally as reasonably possible by preventing
      kvm_mips_check_privilege() from relaying MSA Disabled exceptions from
      guest user mode to the guest kernel, and handling the MSA Disabled
      exception by emulating a Reserved Instruction exception in the guest,
      via a new handle_msa_disabled() KVM callback.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Paul Burton <paul.burton@imgtec.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Cc: <stable@vger.kernel.org> # v3.15+
      98119ad5
    • James Hogan's avatar
      Merge branch '4.1-fp' of git://git.linux-mips.org/pub/scm/ralf/upstream-sfr into kvm_mips_queue · 8e6c9491
      James Hogan authored
      MIPS FP/MSA fixes from the MIPS tree. Includes a fix to ensure that the
      FPU is properly disabled by lose_fpu() when MSA is in use, and Paul
      Burton's "FP/MSA fixes" patchset which is required for FP/MSA support in
      KVM:
      
      > This series fixes a bunch of bugs, both build & runtime, with FP & MSA
      > support. Most of them only affect systems with the new FP modes & MSA
      > support enabled but patch 6 in particular is more general, fixing
      > problems for mips64 systems.
      8e6c9491
    • James Hogan's avatar
      MIPS: MSA: Fix big-endian FPR_IDX implementation · 1f3a2c6e
      James Hogan authored
      The maximum word size is 64-bits since MSA state is saved using st.d
      which stores two 64-bit words, therefore reimplement FPR_IDX using xor,
      and only within each 64-bit word.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/9169/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      1f3a2c6e
    • James Hogan's avatar
      Revert "MIPS: Don't assume 64-bit FP registers for context switch" · 466aec5f
      James Hogan authored
      This reverts commit 02987633.
      
      The basic premise of the patch was incorrect since MSA context
      (including FP state) is saved using st.d which stores two consecutive
      64-bit words in memory rather than a single 128-bit word. This means
      that even with big endian MSA, the FP state is still in the first 64-bit
      word.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/9168/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      466aec5f
    • Paul Burton's avatar
      MIPS: disable FPU if the mode is unsupported · 84ab45b3
      Paul Burton authored
      The expected semantics of __enable_fpu are for the FPU to be enabled
      in the given mode if possible, otherwise for the FPU to be left
      disabled and SIGFPE returned. The FPU was incorrectly being left
      enabled in cases where the desired value for FR was unavailable.
      Without ensuring the FPU is disabled in this case, it would be
      possible for userland to go on to execute further FP instructions
      natively in the incorrect mode, rather than those instructions being
      trapped & emulated as they need to be.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/9167/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      84ab45b3
    • Paul Burton's avatar
      MIPS: prevent FP context set via ptrace being discarded · ac9ad83b
      Paul Burton authored
      If a ptracee has not used the FPU and the ptracer sets its FP context
      using PTRACE_POKEUSR, PTRACE_SETFPREGS or PTRACE_SETREGSET then that
      context will be discarded upon either the ptracee using the FPU or a
      further write to the context via ptrace. Prevent this loss by recording
      that the task has "used" math once its FP context has been written to.
      The context initialisation code that was present for the PTRACE_POKEUSR
      case is reused for the other 2 cases to provide consistent behaviour
      for the different ptrace requests.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/9166/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      ac9ad83b
    • Paul Burton's avatar
      MIPS: Ensure FCSR cause bits are clear after invoking FPU emulator · ad70c13a
      Paul Burton authored
      When running the emulator to handle an instruction that raised an FP
      unimplemented operation exception, the FCSR cause bits were being
      cleared. This is done to ensure that the kernel does not take an FP
      exception when later restoring FP context to registers. However, this
      was not being done when the emulator is invoked in response to a
      coprocessor unusable exception. This happens in 2 cases:
      
        - There is no FPU present in the system. In this case things were
          OK, since the FP context is never restored to hardware registers
          and thus no FP exception may be raised when restoring FCSR.
      
        - The FPU could not be configured to the mode required by the task.
          In this case it would be possible for the emulator to set cause
          bits which are later restored to hardware if the task migrates
          to a CPU whose associated FPU does support its mode requirements,
          or if the tasks FP mode requirements change.
      
      Consistently clear the cause bits after invoking the emulator, by moving
      the clearing to process_fpemu_return and ensuring this is always called
      before the tasks FP context is restored. This will make it easier to
      catch further paths invoking the emulator in future, as will be
      introduced in further patches.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/9165/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      ad70c13a
    • Paul Burton's avatar
      MIPS: clear MSACSR cause bits when handling MSA FP exception · 091be550
      Paul Burton authored
      Much like for traditional scalar FP exceptions, the cause bits in the
      MSACSR register need to be cleared following an MSA FP exception.
      Without doing so the exception will simply be raised again whenever
      the kernel restores MSACSR from a tasks saved context, leading to
      undesirable spurious exceptions. Clear the cause bits from the
      handle_msa_fpe function, mirroring the way handle_fpe clears the
      cause bits in FCSR.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/9164/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      091be550
    • Paul Burton's avatar
      MIPS: wrap cfcmsa & ctcmsa accesses for toolchains with MSA support · e1bebbab
      Paul Burton authored
      Uses of the cfcmsa & ctcmsa instructions were not being wrapped by a
      macro in the case where the toolchain supports MSA, since the arguments
      exactly match a typical use of the instructions. However using current
      toolchains this leads to errors such as:
      
        arch/mips/kernel/genex.S:437: Error: opcode not supported on this processor: mips32r2 (mips32r2) `cfcmsa $5,1'
      
      Thus uses of the instructions must be in the context of a ".set msa"
      directive, however doing that from the users of the instructions would
      be messy due to the possibility that the toolchain does not support
      MSA. Fix this by renaming the macros (prepending an underscore) in order
      to avoid recursion when attempting to emit the instructions, and provide
      implementations for the TOOLCHAIN_SUPPORTS_MSA case which ".set msa" as
      appropriate.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/9163/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      e1bebbab
    • Paul Burton's avatar
      MIPS: remove MSA macro recursion · a3a49810
      Paul Burton authored
      Recursive macros made the code more concise & worked great for the
      case where the toolchain doesn't support MSA. However, with toolchains
      which do support MSA they lead to build failures such as:
      
        arch/mips/kernel/r4k_switch.S: Assembler messages:
        arch/mips/kernel/r4k_switch.S:148: Error: invalid operands `insert.w $w(0+1)[2],$1'
        arch/mips/kernel/r4k_switch.S:148: Error: invalid operands `insert.w $w(0+1)[3],$1'
        arch/mips/kernel/r4k_switch.S:148: Error: invalid operands `insert.w $w((0+1)+1)[2],$1'
        arch/mips/kernel/r4k_switch.S:148: Error: invalid operands `insert.w $w((0+1)+1)[3],$1'
        ...
      
      Drop the recursion from msa_init_all_upper invoking the msa_init_upper
      macro explicitly for each vector register.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/9162/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      a3a49810
    • Paul Burton's avatar
      MIPS: assume at as source/dest of MSA copy/insert instructions · f23ce388
      Paul Burton authored
      Assuming at ($1) as the source or destination register of copy or
      insert instructions:
      
        - Simplifies the macros providing those instructions for toolchains
          without MSA support.
      
        - Avoids an unnecessary move instruction when at is used as the source
          or destination register anyway.
      
        - Is sufficient for the uses to be introduced in the kernel by a
          subsequent patch.
      
      Note that due to a patch ordering snafu on my part this also fixes the
      currently broken build with MSA support enabled. The build has been
      broken since commit c9017757 "MIPS: init upper 64b of vector
      registers when MSA is first used", which this patch should have
      preceeded.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/9161/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      f23ce388
    • Paul Burton's avatar
      MIPS: Push .set mips64r* into the functions needing it · 631afc65
      Paul Burton authored
      The {save,restore}_fp_context{,32} functions require that the assembler
      allows the use of sdc instructions on any FP register, and this is
      acomplished by setting the arch to mips64r2 or mips64r6
      (using MIPS_ISA_ARCH_LEVEL_RAW).
      
      However this has the effect of enabling the assembler to use mips64
      instructions in the expansion of pseudo-instructions. This was done in
      the (now-reverted) commit eec43a22 "MIPS: Save/restore MSA context
      around signals" which led to my mistakenly believing that there was an
      assembler bug, when in reality the assembler was just emitting mips64
      instructions. Avoid the issue for future commits which will add code to
      r4k_fpu.S by pushing the .set MIPS_ISA_ARCH_LEVEL_RAW directives into
      the functions that require it, and remove the spurious assertion
      declaring the assembler bug.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      [james.hogan@imgtec.com: Rebase on v4.0-rc1 and reword commit message to
       reflect use of MIPS_ISA_ARCH_LEVEL_RAW]
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/9612/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      631afc65