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  1. 22 Aug, 2013 1 commit
  3. 21 Aug, 2013 3 commits
    • Kevin Hilman's avatar
      Merge tag 'sunxi-core-for-3.12-2' of https://github.com/mripard/linux into next/soc · fe870ae7
      Kevin Hilman authored 
      Allwinner sunXi core additions for 3.12, take 2

These patches add machine support for the Allwinner A20 and A31 SoCs

* tag 'sunxi-core-for-3.12-2' of https://github.com/mripard/linux:
  ARM: sunxi: Introduce Allwinner A20 support
  ARM: sun6i: Add restart code for the A31
  ARM: sunxi: Add the Allwinner A31 compatible to the machine definition
      fe870ae7
    • Kevin Hilman's avatar
      Merge tag 'sunxi-core-for-3.12' of https://github.com/mripard/linux into next/soc · f7b29518
      Kevin Hilman authored 
      Allwinner sunXi core additions for 3.12

There's not much in this pull request, only a patch removing some dead code.

* tag 'sunxi-core-for-3.12' of https://github.com/mripard/linux:
  ARM: sunxi: Remove Makefile.boot file
Signed-off-by: default avatarKevin Hilman <khilman@linaro.org>
      f7b29518
    • Kevin Hilman's avatar
      Merge tag 'tegra-for-3.12-soc' of... · bfa664f2
      Kevin Hilman authored 
      Merge tag 'tegra-for-3.12-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc

From: Stephen Warren:
ARM: tegra: core SoC enhancements for 3.12

This branch includes a number of enhancements to core SoC support for
Tegra devices. The major new features are:

* Adds a new CPU-power-gated cpuidle state for Tegra114.
* Adds initial system suspend support for Tegra114, initially supporting
  just CPU-power-gating during suspend.
* Adds "LP1" suspend mode support for all of Tegra20/30/114. This mode
  both gates CPU power, and places the DRAM into self-refresh mode.
* A new DT-driven PCIe driver to Tegra20/30. The driver is also moved
  from arch/arm/mach-tegra/ to drivers/pci/host/.

The PCIe driver work depends on the following tag from Thomas Petazzoni:
git://git.infradead.org/linux-mvebu.git mis-3.12.2
... which is merged into the middle of this pull request.

* tag 'tegra-for-3.12-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (33 commits)
  ARM: tegra: disable LP2 cpuidle state if PCIe is enabled
  MAINTAINERS: Add myself as Tegra PCIe maintainer
  PCI: tegra: set up PADS_REFCLK_CFG1
  PCI: tegra: Add Tegra 30 PCIe support
  PCI: tegra: Move PCIe driver to drivers/pci/host
  PCI: msi: add default MSI operations for !HAVE_GENERIC_HARDIRQS platforms
  ARM: tegra: add LP1 suspend support for Tegra114
  ARM: tegra: add LP1 suspend support for Tegra20
  ARM: tegra: add LP1 suspend support for Tegra30
  ARM: tegra: add common LP1 suspend support
  clk: tegra114: add LP1 suspend/resume support
  ARM: tegra: config the polarity of the request of sys clock
  ARM: tegra: add common resume handling code for LP1 resuming
  ARM: pci: add ->add_bus() and ->remove_bus() hooks to hw_pci
  of: pci: add registry of MSI chips
  PCI: Introduce new MSI chip infrastructure
  PCI: remove ARCH_SUPPORTS_MSI kconfig option
  PCI: use weak functions for MSI arch-specific functions
  ARM: tegra: unify Tegra's Kconfig a bit more
  ARM: tegra: remove the limitation that Tegra114 can't support suspend
  ...
Signed-off-by: default avatarKevin Hilman <khilman@linaro.org>
      bfa664f2
  5. 19 Aug, 2013 4 commits
  7. 16 Aug, 2013 4 commits
    • Maxime Ripard's avatar
      ARM: sunxi: Introduce Allwinner A20 support · d18fd944
      Maxime Ripard authored 
      The Allwinner A20 is a dual-core Cortex-A7-based SoC. It is
pin-compatible with the A10, and re-uses most of the IPs found in it,
plus some additional ones like a Gigabit Ethernet controller.
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
      d18fd944
    • Maxime Ripard's avatar
      ARM: sun6i: Add restart code for the A31 · 06d71bcf
      Maxime Ripard authored 
      The Allwinner A31 has a different watchdog, with a slightly different
register layout, that requires a different restart code.
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
      06d71bcf
    • Maxime Ripard's avatar
      ARM: sunxi: Add the Allwinner A31 compatible to the machine definition · 2d794510
      Maxime Ripard authored 
      The Allwinner A31 is a quad-Cortex-A7 based SoC, which shares a lot of
IPs with the previous SoCs from Allwinner, like the PIO, I2C, UARTs,
timers, watchdog IPs, but also differs by dropping the WEMAC ethernet
controller and most notably dropping the in-house IRQ controller in
favor of a ARM GIC one.
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
      2d794510
    • Olof Johansson's avatar
      Merge tag 'drivers-3.12' of git://git.infradead.org/linux-mvebu into next/soc · f668adeb
      Olof Johansson authored 
      From Jason Cooper:
mvebu drivers changes for v3.12

 - MBus devicetree bindings
 - devbus update for address decoding window, cleanup

* tag 'drivers-3.12' of git://git.infradead.org/linux-mvebu: (35 commits)
  memory: mvebu-devbus: Remove unused variable
  ARM: mvebu: Relocate PCIe node in Armada 370 RD board
  ARM: mvebu: Fix AXP-WiFi-AP DT for MBUS DT binding
  ARM: mvebu: add support for the AXP WiFi AP board
  ARM: mvebu: use dts pre-processor for mv78230
  PCI: mvebu: Adapt to the new device tree layout
  bus: mvebu-mbus: Add devicetree binding
  ARM: kirkwood: Relocate PCIe device tree nodes
  ARM: kirkwood: Introduce MBUS_ID
  ARM: kirkwood: Introduce MBus DT node
  ARM: kirkwood: Use the preprocessor on device tree files
  ARM: kirkwood: Split DT and legacy MBus initialization
  ARM: mvebu: Relocate Armada 370/XP PCIe device tree nodes
  ARM: mvebu: Relocate Armada 370/XP DeviceBus device tree nodes
  ARM: mvebu: Add BootROM to Armada 370/XP device tree
  ARM: mvebu: Add MBus to Armada 370/XP device tree
  ARM: mvebu: Use the preprocessor on Armada 370/XP device tree files
  ARM: mvebu: Initialize MBus using the DT binding
  ARM: mvebu: Remove the harcoded BootROM window allocation
  bus: mvebu-mbus: Factorize Armada 370/XP data structures
  ...
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
      f668adeb
  9. 14 Aug, 2013 7 commits
  11. 13 Aug, 2013 15 commits
  13. 12 Aug, 2013 6 commits
    • Joseph Lo's avatar
      ARM: tegra: add LP1 suspend support for Tegra114 · e9f62449
      Joseph Lo authored 
      The LP1 suspend mode will power off the CPU, clock gated the PLLs and put
SDRAM to self-refresh mode. Any interrupt can wake up device from LP1. The
sequence when LP1 suspending:

* tunning off L1 data cache and the MMU
* storing some EMC registers, DPD (deep power down) status, clk source of
  mselect and SCLK burst policy
* putting SDRAM into self-refresh
* switching CPU to CLK_M (12MHz OSC)
* tunning off PLLM, PLLP, PLLA, PLLC and PLLX
* switching SCLK to CLK_S (32KHz OSC)
* shutting off the CPU rail

The sequence of LP1 resuming:

* re-enabling PLLM, PLLP, PLLA, PLLC and PLLX
* restoring the clk source of mselect and SCLK burst policy
* setting up CCLK burst policy to PLLX
* restoring DPD status and some EMC registers
* resuming SDRAM to normal mode
* jumping to the "tegra_resume" from PMC_SCRATCH41

Due to the SDRAM will be put into self-refresh mode, the low level
procedures of LP1 suspending and resuming should be copied to
TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K) when suspending. Before
restoring the CPU context when resuming, the SDRAM needs to be switched
back to normal mode. And the PLLs need to be re-enabled, SCLK burst policy
be restored. Then jumping to "tegra_resume" that was expected to be stored
in PMC_SCRATCH41 to restore CPU context and back to kernel.

Based on the work by: Bo Yan <byan@nvidia.com>
Signed-off-by: default avatarJoseph Lo <josephl@nvidia.com>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
      e9f62449
    • Joseph Lo's avatar
      ARM: tegra: add LP1 suspend support for Tegra20 · 731a9274
      Joseph Lo authored 
      The LP1 suspend mode will power off the CPU, clock gated the PLLs and put
SDRAM to self-refresh mode. Any interrupt can wake up device from LP1. The
sequence when LP1 suspending:

* tunning off L1 data cache and the MMU
* putting SDRAM into self-refresh
* storing some EMC registers and SCLK burst policy
* switching CPU to CLK_M (12MHz OSC)
* switching SCLK to CLK_S (32KHz OSC)
* tunning off PLLM, PLLP and PLLC
* shutting off the CPU rail

The sequence of LP1 resuming:

* re-enabling PLLM, PLLP, and PLLC
* restoring some EMC registers and SCLK burst policy
* setting up CCLK burst policy to PLLP
* resuming SDRAM to normal mode
* jumping to the "tegra_resume" from PMC_SCRATCH41

Due to the SDRAM will be put into self-refresh mode, the low level
procedures of LP1 suspending and resuming should be copied to
TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K) when suspending. Before
restoring the CPU context when resuming, the SDRAM needs to be switched
back to normal mode. And the PLLs need to be re-enabled, SCLK burst policy
be restored, CCLK burst policy be set in PLLP. Then jumping to
"tegra_resume" that was expected to be stored in PMC_SCRATCH41 to restore
CPU context and back to kernel.

Based on the work by:
Colin Cross <ccross@android.com>
Gary King <gking@nvidia.com>
Signed-off-by: default avatarJoseph Lo <josephl@nvidia.com>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
      731a9274
    • Joseph Lo's avatar
      ARM: tegra: add LP1 suspend support for Tegra30 · e7a932b1
      Joseph Lo authored 
      The LP1 suspend mode will power off the CPU, clock gated the PLLs and put
SDRAM to self-refresh mode. Any interrupt can wake up device from LP1. The
sequence when LP1 suspending:

* tunning off L1 data cache and the MMU
* storing some EMC registers, DPD (deep power down) status, clk source of
  mselect and SCLK burst policy
* putting SDRAM into self-refresh
* switching CPU to CLK_M (12MHz OSC)
* tunning off PLLM, PLLP, PLLA, PLLC and PLLX
* switching SCLK to CLK_S (32KHz OSC)
* shutting off the CPU rail

The sequence of LP1 resuming:

* re-enabling PLLM, PLLP, PLLA, PLLC and PLLX
* restoring the clk source of mselect and SCLK burst policy
* setting up CCLK burst policy to PLLX
* restoring DPD status and some EMC registers
* resuming SDRAM to normal mode
* jumping to the "tegra_resume" from PMC_SCRATCH41

Due to the SDRAM will be put into self-refresh mode, the low level
procedures of LP1 suspending and resuming should be copied to
TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K) when suspending. Before
restoring the CPU context when resuming, the SDRAM needs to be switched
back to normal mode. And the PLLs need to be re-enabled, SCLK burst policy
be restored, CCLK burst policy be set in PLLX. Then jumping to
"tegra_resume" that was expected to be stored in PMC_SCRATCH41 to restore
CPU context and back to kernel.

Based on the work by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: default avatarJoseph Lo <josephl@nvidia.com>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
      e7a932b1
    • Joseph Lo's avatar
      ARM: tegra: add common LP1 suspend support · 95872f42
      Joseph Lo authored 
      The LP1 suspending mode on Tegra means CPU rail off, devices and PLLs are
clock gated and SDRAM in self-refresh mode. That means the low level LP1
suspending and resuming code couldn't be run on DRAM and the CPU must
switch to the always on clock domain (a.k.a. CLK_M 12MHz oscillator). And
the system clock (SCLK) would be switched to CLK_S, a 32KHz oscillator.
The LP1 low level handling code need to be moved to IRAM area first. And
marking the LP1 mask for indicating the Tegra device is in LP1. The CPU
power timer needs to be re-calculated based on 32KHz that was originally
based on PCLK.

When resuming from LP1, the LP1 reset handler will resume PLLs and then
put DRAM to normal mode. Then jumping to the "tegra_resume" that will
restore full context before back to kernel. The "tegra_resume" handler
was expected to be found in PMC_SCRATCH41 register.

This is common LP1 procedures for Tegra, so we do these jobs mainly in
this patch:
* moving LP1 low level handling code to IRAM
* marking LP1 mask
* copying the physical address of "tegra_resume" to PMC_SCRATCH41
* re-calculate the CPU power timer based on 32KHz
Signed-off-by: default avatarJoseph Lo <josephl@nvidia.com>
[swarren, replaced IRAM_CODE macro with IO_ADDRESS(TEGRA_IRAM_CODE_AREA)]
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
      95872f42
    • Joseph Lo's avatar
      clk: tegra114: add LP1 suspend/resume support · 0017f447
      Joseph Lo authored 
      When the system suspends to LP1, the CPU clock source is switched to
CLK_M (12MHz Oscillator) during suspend/resume flow. The CPU clock
source is controlled by the CCLKG_BURST_POLICY register, and hence this
register must be restored during LP1 resume.

Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: default avatarJoseph Lo <josephl@nvidia.com>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
      0017f447
    • Joseph Lo's avatar
      ARM: tegra: config the polarity of the request of sys clock · 444f9a80
      Joseph Lo authored 
      When suspending to LP1 mode, the SYSCLK will be clock gated. And different
board may have different polarity of the request of SYSCLK, this patch
configure the polarity from the DT for the board.
Signed-off-by: default avatarJoseph Lo <josephl@nvidia.com>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
      444f9a80
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