1. 15 May, 2012 1 commit
  2. 14 May, 2012 1 commit
  3. 12 May, 2012 1 commit
  4. 10 May, 2012 4 commits
  5. 09 May, 2012 2 commits
    • Sebastian Andrzej Siewior's avatar
      ARM: davinci: optimize the DMA ISR · bcd59b0f
      Sebastian Andrzej Siewior authored
      The ISR does quiete a lot of hw access which could be avoided. First it
      checks for a pending interrupt by reading alteast one register. Then it
      checks for the "activated" slots by reading another register. This is
      more or a less a must.
      Now, once it found an active slot it does the same two reads again.
      After that it "knows" that there must be a pending transfer however it
      cross checks with the other register. There are 32 bit in an interger
      which are polled instead of considering only the set bits and ignoring
      those which are zero. This performs atleast 32 reads which could be
      avoided. In case of a first match it does another read.
      This patch reorganizes the access by re-using the register which have
      been read and then uses ffs() to find the matching slot instead looping
      over it. By doing this we get rid of the last (32 + 2 + hits) reads.
      
      It is possible however that by really busy bank0 we never get to handle
      bank1. If this is a problem, we could try to handle bank1 after we are
      done with bank0 to check if there are any outstanding transfers.
      
      To put some numbers on this, this is from spi transfer via spidev. The
      first column is the number of total transfers, the time stamp is taken
      before and after the ioctl():
      
      |10000, min: 542us      avg: 591us
      |20000, min: 542us      avg: 592us
      |30000, min: 542us      avg: 592us
      |40000, min: 542us      avg: 585us
      |50000, min: 542us      avg: 593us
      
      The same test case with the patch applied
      |10000, min: 444us      avg: 493us
      |20000, min: 444us      avg: 491us
      |30000, min: 444us      avg: 489us
      |40000, min: 444us      avg: 491us
      |50000, min: 444us      avg: 492us
      
      that is almost 100us that just went away.
      Signed-off-by: default avatarSebastian Andrzej Siewior <bigeasy@linutronix.de>
      Signed-off-by: default avatarSekhar Nori <nsekhar@ti.com>
      bcd59b0f
    • Uwe Kleine-König's avatar
      ARM: davinci: implement DEBUG_LL port choice · 477099f1
      Uwe Kleine-König authored
      Apart from the necessity to do this change for multi-platform kernels
      the previous logic depended on the zImage decompressor to write the
      physical and virtual address to a magic memory location.
      If the decompressor is unused or not correctly configured for the
      current machid, the addruart macro was an infinite loop. Moreover
      debugging the early zImage code was not possible either.
      Signed-off-by: default avatarUwe Kleine-König <u.kleine-koenig@pengutronix.de>
      [nsekhar@ti.com: add braces in _DEBUG_LL_ENTRY() macro to fix checkpatch
      error. Fix debug port choice config dependency for traditional DaVincis.
      Modify debug port config names and add help text.]
      Signed-off-by: default avatarSekhar Nori <nsekhar@ti.com>
      477099f1
  6. 08 May, 2012 2 commits
  7. 06 May, 2012 5 commits
  8. 05 May, 2012 10 commits
  9. 04 May, 2012 14 commits