- 14 Oct, 2008 5 commits
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Benjamin Herrenschmidt authored
The detection of the IBM "Python" PCI host bridge on IBM CHRP machines such as old RS6000 was broken when we changed of_device_is_compatible() from strncasecmp to strcasecmp (dropped the "n" variant) due to the way IBM encodes the chip version. We fix that by instead doing a match on the model property like we do for others bridges in that file. It should be good enough for those machines. If yours is still broken, let me know. Signed-off-by:Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Benjamin Herrenschmidt authored
prom_init was changed to take a new argument, the address where the kernel is loaded, which is now used to copy the SMP spin loop down before use. However, only head_64.S was adapted to pass this new value, not head_32.S, thus breaking SMP boot on 32-bit SMP CHRP machines. Signed-off-by: -
Benjamin Herrenschmidt authored
The new merged DMA code will try to access isa_bridge_pcidev when trying to DMA to/from legacy devices. This is however only defined on 64-bit. Fixes this for now by adding the variable, even if it stays NULL. In the long run, we'll make isa-bridge.c common to 32 and 64-bit. Signed-off-by: -
Benjamin Herrenschmidt authored
When the powerpc PCI layer is not configured to re-assign everything, it currently fails to detect that a PCI to PCI bridge has been left unassigned by the firmware and tries to allocate resource for the default window values in the bridge (0...X) (with the notable exception of a hack we have in there that detects some Apple firmware unassigned bridge resources). This results in resource allocation failures, which are generally fixed up later on but it causes scary warnings in the logs and we have seen the fixup code fall over in some circumstances (a different issue to fix as well). This code improves that by providing a more complete & useful function to intuit that a bridge was left unassigned by the firmware, and thus force a full re-allocation by the PCI code without trying to allocate the existing useless resources first. The algorithm we use basically considers unassigned a window that starts at 0 (PCI address) if the corresponding address space enable bit is not set. In addition, for memory space, it considers such a resource unassigned also if the host bridge isn't configured to forward cycles to address 0 (ie, the resource basically overlaps main memory). This fixes a range of problems with things like Bare-Metal support on pSeries machines, or attempt to use partial firmware PCI setup. Signed-off-by: -
Christian Borntraeger authored
commit 611e097d Author: Christian Borntraeger <borntraeger@de.ibm.com> hvc_console: rework setup to replace irq functions with callbacks introduced a spinlock recursion problem. The notifier_del is called with a lock held, and in turns calls free_irq which then complains when manipulating procfs. This fixes it by moving the call to the notifier to outside of the locked section. Signed-off-by: Christian Borntraeger<borntraeger@de.ibm.com> Signed-off-by:
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- 13 Oct, 2008 35 commits
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David Gibson authored
The typesafe version of the powerpc pagetable handling (with USE_STRICT_MM_TYPECHECKS defined) has bitrotted again. This patch makes a bunch of small fixes to get it back to building status. It's still not enabled by default as gcc still generates worse code with it for some reason. Signed-off-by:
David Gibson <david@gibson.dropbear.id.au> Signed-off-by:
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Sebastian Andrzej Siewior authored
The "phys" argument to machine_init() isn't used and isn't likely to ever be so let's remove it. Signed-off-by:
Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by:
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Benjamin Herrenschmidt authored
After Becky's work we can almost have different DMA offsets between on-chip devices and PCI. Almost because there's a problem with the non-coherent DMA code that basically ignores the programmed offset to use the global one for everything. This fixes it. Signed-off-by: -
Benjamin Herrenschmidt authored
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Benjamin Herrenschmidt authored
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Anton Vorontsov authored
The fsl_upm nand driver fails to build because fsl_lbc_lock isn't exported, the lock is needed by the inlined fsl_upm_run_pattern() function: ERROR: "fsl_lbc_lock" [drivers/mtd/nand/fsl_upm.ko] undefined! Dave Jones purposed to export the lock, but it is better to just uninline the fsl_upm_run_pattern(). When uninlined we also no longer need the exported fsl_lbc_regs, and both fsl_lbc_lock and fsl_lbc_regs could be marked static. While at it, also add some missing includes that we should have included explicitly. Reported-by:
Dave Jones <davej@redhat.com> Signed-off-by:
Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Anton Vorontsov authored
The StMicro NAND chip (512Mbit, 64MB) is connected to the local bus, the first local bus' user-programmable machine is configured by the firmware to work with NAND chips. QE GPIO pin is used to poll the NAND's Ready-Not-Busy signal. Signed-off-by:
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Martyn Welch authored
Support for the SBC610 VPX Single Board Computer from GE Fanuc (PowerPC MPC8641D). This patch adds support for the registers held in the devices main FPGA, exposing extra information about the revision of the board through cpuinfo. Signed-off-by:
Martyn Welch <martyn.welch@gefanuc.com> Signed-off-by:
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Anton Vorontsov authored
On MPC8349E-mITX, MPC8315E-RDB and MPC837x-RDB boards there is a Freescale MC9S08QG8 (MCU) chip with the custom firmware pre-programmed. The chip is used to power-off the board by the software, and to control some GPIO pins. Signed-off-by:
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Timur Tabi authored
The Freescale Elo DMA driver binds to all DMA channels in the device tree that are compatible with "fsl,eloplus-dma-channel". This conflicts with the sound drivers for the MPC8610 HPCD. On this board, the SSI uses two DMA channels and therefore those channels are not available for general purpose use. We change the compatible properties for these channels "fsl,ssi-dma-channel". This works because the sound drivers don't actually check the compatible property when it grabs channels. Signed-off-by:
Timur Tabi <timur@freescale.com> Signed-off-by:
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Timur Tabi authored
The "fsl,ssi-dma-channel" compatible property is used to specify a DMA channel on the Freescale Elo DMA controller that should be used exclusively by the Freescale SSI audio controller. When a property is marked as such, the Elo DMA driver will ignore it, and so it will be available for the sound drivers. Signed-off-by:
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Timur Tabi authored
Because CHRP and PMAC are by default enabled, several non-CHRP and non-PMAC PowerPC defconfigs will have these Kconfig options set erroneously. Signed-off-by:
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Anton Vorontsov authored
of/base.c matches on the first (most specific) entries, which isn't quite practical but it was discussed[1] that this won't change. The bindings specifies verbose information for the devices, but it doesn't fit in the I2C ID's 20 characters limit. The limit won't change[2], and the bindings won't change either as they're correct. So we have to put an exception for the MPC8349E-mITX-compatible MCUs. Signed-off-by:
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Anton Vorontsov authored
The RTC is sitting on the I2C1 bus at address 0x68. RTC interrupt signal is connected to the IPIC's EXT3 interrupt line. Signed-off-by:
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Timur Tabi authored
Early versions of the Freescale DIU framebuffer driver depended on a bootmem allocation of memory for the video buffer. The need for this feature was removed in commit 6b51d51a, so now we can remove the platform-specific code that allocated that memory. Signed-off-by:
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Milton Miller authored
b38fd42f added false dependencys to order the load of upper and lower halfs of the pte, but only adjusted whitespace instead of deleting the old load in the iside handler, letting the hardware see the non-dependent load. This patch removes the extra load. Signed-off-by:
Milton Miller <miltonm@bga.com> Signed-off-by:
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John Rigby authored
Uses mpc83xx_add_bridge in fsl_pci.c Adds second register tuple to pci node register property as done for 83xx device trees in a previous patch. Signed-off-by:
John Rigby <jrigby@freescale.com> Acked-by:
Grant Likely <grant.likely@secretlab.ca> Signed-off-by:
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John Rigby authored
Modify mpc83xx_add_bridge to get config space register base address from the device tree instead of immr + hardcoded offset. 83xx pci nodes have this change: register properties now contain two address length tuples: First is the pci bridge register base, this has always been there. Second is the config base, this is new. This is documented in dts-bindings/fsl/83xx-512x-pci.txt The changes accomplish these things: mpc83xx_add_bridge no longer needs to call get_immrbase it uses hard coded addresses if the second register value is missing Signed-off-by: -
John Rigby authored
The class of the MPC5121 pci host bridge is PCI_CLASS_BRIDGE_OTHER while other freescale host bridges have class set to PCI_CLASS_PROCESSOR_POWERPC. This patch makes fixup_hide_host_resource_fsl match PCI_CLASS_BRIDGE_OTHER in addition to PCI_CLASS_PROCESSOR_POWERPC. Signed-off-by:
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Anton Vorontsov authored
In the standalone setup the board's CPLD disables the PCI internal arbiter, thus any access to the PCI bus will hang the board. The common way to disable particular devices in the device tree is to put the "status" property with any value other than "ok" or "okay" into the device node we want to disable. So, when there is no PCI arbiter on the bus the u-boot adds status = "broken (no arbiter)" property into the PCI controller's node, and so marks the PCI controller as unavailable. Signed-off-by:
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Anton Vorontsov authored
Specifying user-selectable option in the qe_lib/Kconfig was a bad idea because the qe_lib/Kconfig is included into the top level Kconfig, and thus the QE_GPIO option appears at the top level menu. This patch effectively moves the QE_GPIO option under the platform menu instead. Signed-off-by:
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Timur Tabi authored
Modify the Kconfig so that Freescale QUICC Engine (QE) support is a selectable option, thereby allowing users to compile kernels without any QE support. The drawback is that QE support is now disabled by default on platforms that have a QE, and so a defconfig is needed to enable QE and QE devices (like UCC GETH). Fortunately, all the current relevant defconfigs do that already. Signed-off-by:
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Martyn Welch authored
Support for the SBC610 VPX Single Board Computer from GE Fanuc (PowerPC MPC8641D). A number of MPC8641D based route interrupts for on-board interrupts through a FPGA based interrupt controller, which is chained with the MPC8641D's mpic. This patch provides a basic driver to allow basic routing of interrupts to the mpic. Signed-off-by:
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Kumar Gala authored
Add interrupt info to the MPC8536DS .dts for the RTC Signed-off-by: -
Milton Miller authored
The comment in the code was asking "Do we have to do this?", and according to x86 and s390 the answer is no, the scheduler will do it before calling the arch hook. Signed-off-by:
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Milton Miller authored
A single full sync (mb()) is requrired to order the mmio to the qirr reg with the set or clear of the message word. However, test_and_clear_bit has the effect of smp_mb() and we are not doing any other io from here, so we don't need a mb per bit processed. Signed-off-by:
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Milton Miller authored
Several printks were broken at word boundaries for line length. Some even referred to old function names. Using __func__ and changing the text slightly for the format allows these printk formats to fit on one line. Signed-off-by:
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Milton Miller authored
It is physically per-cpu, and we want the irq layer to treat it that way. Signed-off-by:
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Milton Miller authored
EOI normally has the side effect of returning the cpu to the base priority to recieve the next interrupt. This is actually controlled by the top byte of the xirr register. When we are exiting the kernel in kexec we must eoi the ipi for the next kernel because we never return from the handler, but we want to leave interrupt delivery blocked until the next kernel takes action. Since the hardware ipi vector is fixed, its easiest to just do the eoi explicitly. Signed-off-by:
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Milton Miller authored
This factors out processors joining and unjoining the Global Interrupt Queue into a separate function. There is a bit of math to calculate the arguments to rtas to join or leave the global interrupt queue, and a warning on failure afterwards. Make a helper for the 3 callers. Signed-off-by:
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Milton Miller authored
We only need to check the ibm,interrupt-server#-size property once, not once per global server and thread. We can use !CONFIG_SMP cpu masks and hard_smp_processor_id() to avoid an ifdef. Put the node when breaking out of the loop on lpar systems. Signed-off-by:
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Milton Miller authored
Trim unneeded includes from xics.c. We don't use signals or gfp flags, we use only OF functions and don't need prom, and the 8259 is now handled by our caller. Signed-off-by:
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Milton Miller authored
The xirr is 32 bits in hardware, but the hypervisor requries the upper bits of the register to be clear on the hcall. By changing the type from signed to unsigned int we can drop masking it back to 32 bits. Signed-off-by:
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Milton Miller authored
Now that xics_update_irq_servers is called only from init and hotplug code, it becomes possible to clean up the ordering of functions in the file, grouping them but the interfaces they implement. Signed-off-by:
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Milton Miller authored
xics supports only one ipi per cpu, and expects software to use some queue to know why the interrupt was sent. In Linux, we use a an array of bitmaps indexed by cpu to identify the message. Currently the bits are set in smp.c and decoded in xics.c, with the data structure in a header file. Consolidate the code in xics.c similar to mpic and other interrupt controllers. Also, while making the the array static, the message word doesn't need to be volatile as set_bit and test_clear_bit take care of it for us, and put it under ifdef smp. Signed-off-by:
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