- 15 Apr, 2016 15 commits
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Stephen Boyd authored
This flag is a no-op now. Remove usage of the flag. Cc: Guo Zeng <Guo.Zeng@csr.com> Cc: Barry Song <Baohua.Song@csr.com> Signed-off-by:Stephen Boyd <sboyd@codeaurora.org>
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Stephen Boyd authored
This flag is a no-op now. Remove usage of the flag. Cc: Chao Xie <chao.xie@marvell.com> Signed-off-by: -
Stephen Boyd authored
This flag is a no-op now. Remove usage of the flag. Cc: Carlo Caione <carlo@caione.org> Signed-off-by: -
Stephen Boyd authored
* clk-artpec6: clk: add artpec-6 clock controller clk: add device tree binding for Artpec-6 clock controller
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Lars Persson authored
Add a driver for the main clock controller of the Artpec-6 Soc. Signed-off-by:
Lars Persson <larper@axis.com> [sboyd@codeaurora.org: Reformatted driver structure and of match] Signed-off-by:
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Lars Persson authored
Add device tree documentation for the main clock controller in the Artpec-6 SoC. Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Suman Anna authored
Commit 7aba4f52 ("clk: ti: dflt: fix enable_reg validity check") fixed a validation check by using an IS_ERR() macro within the existing unlikely expression, but IS_ERR() macro already has an unlikely inside it, so get rid of the redundant unlikely macro from the validation check. Reported-by:
Suman Anna <s-anna@ti.com> Signed-off-by:
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Stephen Boyd authored
Merge tag 'v4.7-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull rockchip clk updates from Heiko Stuebner: This is first big chunk of Rockchip clock-related changes for 4.7. Main change is probably the added support for the new rk3399 soc and necessary infrastructure changes surrounding it. The biggest chunk is probably that clock code is now able to handle multiple clock providers in one system, as the rk3399 has two of those. A general one and another smaller one in a separate power domain. The rk3399 also uses another new pll type. Thankfully it just fits nicely into our current structure. It also needs some parts like the cpuclk mux parameters to be a bit more flexible and an new fractional divider subtype without gate. Apart from this big change we have some more fixes and removal of forgotten variables. * tag 'v4.7-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: add clock controller for the RK3399 dt-bindings: add bindings for rk3399 clock controller clk: rockchip: add dt-binding header for rk3399 clk: rockchip: release io resource when failing to init clk clk: rockchip: remove redundant checking of device_node clk: rockchip: fix warning reported by kernel-doc clk: rockchip: remove mux_core_reg from rockchip_cpuclk_reg_data clk: rockchip: add new pll-type for rk3399 and similar socs clk: rockchip: Add support for multiple clock providers clk: rockchip: allow varying mux parameters for cpuclk pll-sources clk: rockchip: add a COMPOSITE_FRACMUX_NOGATE type
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Stephen Boyd authored
Merge branch 'clk-renesas-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull renesas clk driver updates from Geert Uytterhoeven: - Support for the PWM module clock and watchdog related clocks on R-Car H3, - Cleanups and clarifications. * 'clk-renesas-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: mstp: Clarify cpg_mstp_{at,de}tach_dev() domain parameter clk: renesas: cpg-mssr: Drop check for CONFIG_PM_GENERIC_DOMAINS_OF clk: renesas: mstp: Drop check for CONFIG_PM_GENERIC_DOMAINS_OF clk: renesas: r8a7795: add RWDT clock clk: renesas: r8a7795: add R clk clk: renesas: r8a7795: add OSC and RINT clocks clk: renesas: cpg-mssr: add generic support for read-only DIV6 clocks clk: renesas: r8a7795: make SD clk definition specific for GEN3 clk: renesas: r8a7795: add PWM clock
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Stephen Boyd authored
Merge tag 'imx-clk-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next The i.MX clock update for 4.7: - Register SAI clk as shared clocks to support SAI audio on i.MX6SX - Add the missing ckil clock for i.MX7 - Update clk-gate2 and vf610 clock driver to prepare for suspend support on VF610 - Fix DCU clock configurations and add TCON ipg clock to support DRM display on VF610 * tag 'imx-clk-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: clk: imx: vf610: fix whitespace in vf610-clock.h clk: imx: vf610: add TCON ipg clock clk: imx: vf610: fix DCU clock tree clk: imx: add ckil clock for i.MX7 clk: imx: vf610: add suspend/resume support clk: imx: vf610: add WKPU unit clk: imx: vf610: leave DDR clock on clk: imx: clk-gate2: allow custom gate configuration clk: imx6sx: Register SAI clocks as shared clocks
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git://linuxtv.org/snawrocki/samsungStephen Boyd authored
Pull samsung clk updates from Sylwester Nawrocki: This includes addition of some missing clock tree definitions (UART, MMC2 clocks) for exynos3250 SoC and exporting of IDs for exynos543x SoC AMBA AXI bus clocks needed for bus frequency scaling. * tag 'clk-v4.7-samsung' of git://linuxtv.org/snawrocki/samsung: clk: samsung: exynos542x: Add the clock id for ACLK dt-bindings: clock: Add the clock id for ACLK clock of Exynos542x SoC clk: samsung: exynos3250: Add MMC2 clock clk: samsung: exynos3250: Add UART2 clock dt-bindings: Add the clock id of UART2 and MMC2 for Exynos3250
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Finley Xiao authored
When changing the clock-rate, currently a new parent is set first and a divider adapted thereafter. This may result in the clock-rate overflowing its target rate for a short time if the new parent has a higher rate than the old parent. While this often doesn't produce negative effects, it can affect components in a voltage-scaling environment, like the GPU on the rk3399 socs, where the voltage than simply is to low for the temporarily to high clock rate. For general clock hirarchies this may need more extensive adaptions to the common clock-framework, but at least for composite clocks having both parent and rate settings it is easy to create a short-term solution to make sure the clock-rate does not overflow the target. Signed-off-by:
Finley Xiao <finley.xiao@rock-chips.com> Reviewed-by:
Heiko Stuebner <heiko@sntech.de> Signed-off-by:
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Sylwester Nawrocki authored
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Chanwoo Choi authored
This patch adds the clock id for ACLK clock which is source clock of AMBA AXI bus. This clock should be handled in the bus frequency scaling driver. Signed-off-by:
Chanwoo Choi <cw00.choi@samsung.com> Tested-by:
Markus Reichl <m.reichl@fivetechno.de> Tested-by:
Anand Moon <linux.amoon@gmail.com> Reviewed-by:
Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by:
Sylwester Nawrocki <s.nawrocki@samsung.com>
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Chanwoo Choi authored
This patch adds the clock id for ACLK clock of Exynos542x SoC. ACLK clock means the source clock of AMBA AXI bus. This clock id should be used for Bus frequency scaling. Signed-off-by:
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- 12 Apr, 2016 3 commits
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Shawn Guo authored
There is whitespace in VF610_CLK_OCOTP line. Fix it. Signed-off-by:Shawn Guo <shawnguo@kernel.org>
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Stefan Agner authored
Add the ipg (bus) clock for the TCON modules (Timing Controller). This module is required by the new DCU DRM driver, since the display signals pass through TCON. Signed-off-by:
Stefan Agner <stefan@agner.ch> Signed-off-by:
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Stefan Agner authored
Similar to an earlier fix for the SAI clocks, the DCU clock hierarchy mixes the bus clock with the display controllers pixel clock. Tests have shown that the gates in CCM_CCGR3/9 registers do not control the DCU pixel clock, but only the register access clock (bus clock). Fix this by defining the parent clock of VF610_CLK_DCUx to be the bus clock (ipg_bus). Since the clock has not been used far, there are no further changes needed. Signed-off-by:
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- 09 Apr, 2016 3 commits
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Lee Jones authored
This call matches clocks which have been marked as critical in DT and sets the appropriate flag. These flags can then be used to mark the clock core flags appropriately prior to registration. Legacy bindings requiring this feature must add the clock-critical property to their binding descriptions, as it is not a part of common-clock binding. Cc: devicetree@vger.kernel.org Signed-off-by:
Lee Jones <lee.jones@linaro.org> Reviewed-by:
Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1455225554-13267-4-git-send-email-mturquette@baylibre.com
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Lee Jones authored
Signed-off-by:
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Lee Jones authored
Critical clocks are those which must not be gated, else undefined or catastrophic failure would occur. Here we have chosen to ensure the prepare/enable counts are correctly incremented, so as not to confuse users with enabled clocks with no visible users. Signed-off-by:
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- 07 Apr, 2016 3 commits
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Geert Uytterhoeven authored
Make it clear that the "domain" parameter of the cpg_mstp_attach_dev() and cpg_mstp_detach_dev() functions is not used. The cpg_mstp_attach_dev() and cpg_mstp_detach_dev() callbacks are not only used by the CPG/MSTP Clock Domain driver, but also by the R-Mobile SYSC PM Domain driver. Signed-off-by:Geert Uytterhoeven <geert+renesas@glider.be>
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Geert Uytterhoeven authored
As of commit 71d076ce ("ARM: shmobile: Enable PM and PM_GENERIC_DOMAINS for SoCs with PM Domains"), CONFIG_PM_GENERIC_DOMAINS_OF is always enabled for SoCs with a CPG/MSSR block. Signed-off-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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Geert Uytterhoeven authored
As of commit 71d076ce ("ARM: shmobile: Enable PM and PM_GENERIC_DOMAINS for SoCs with PM Domains"), CONFIG_PM_GENERIC_DOMAINS_OF is always enabled for SoCs with MSTP clocks. Signed-off-by:
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- 06 Apr, 2016 5 commits
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Gary Bisson authored
Add the necessary clock to use the ckil on i.MX7. Inspired from the following patch: https://github.com/boundarydevices/linux-imx6/commit/b80e8271Signed-off-by:
Troy Kisky <troy.kisky@boundarydevices.com> Signed-off-by:
Gary Bisson <gary.bisson@boundarydevices.com> Signed-off-by:
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Wolfram Sang authored
Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by:
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Wolfram Sang authored
R can select between two parents. We deal with it like this: During initialization, check if EXTALR is populated. If so, use it for R. If not, use R_Internal. clk_mux doesn't help here because we don't want to switch parents depending on the clock rate. The clock rate (and source) should stay constant for the watchdog, so I think a setup like this during initialization makes sense. Signed-off-by:
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Wolfram Sang authored
Signed-off-by:
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Wolfram Sang authored
Gen3 has two clocks (OSC and R) which look like a DIV6 clock but their divider value is read-only and depends on MD pins at bootup. Add support for such clocks by reading the value and adding a fixed clock. Signed-off-by:
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- 02 Apr, 2016 2 commits
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Thomas Petazzoni authored
This commit adds the Device Tree binding documentation for the system controller found in Marvell AP806 HW block, which is one of the core HW blocks of the 64-bits Marvell Armada 7K/8K family. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by:
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Thomas Petazzoni authored
The drivers/clk/mvebu directory is only being built when CONFIG_PLAT_ORION=y. As we are going to support additional mvebu platforms in drivers/clk/mvebu, which don't have CONFIG_PLAT_ORION=y, we need to recurse into this directory regardless of the value of CONFIG_PLAT_ORION. Since all files in drivers/clk/mvebu/ are already conditionally compiled depending on various Kconfig options, we can recurse unconditionally into drivers/clk/mvebu without any other change. Signed-off-by:
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- 31 Mar, 2016 8 commits
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Chanwoo Choi authored
This patch add the MMC2 clocks (mux, divider, gate) of Exynos3250 SoC. Signed-off-by:
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Pankaj Dubey authored
This patch add the UART2 clocks (mux, divider, gate) of Exynos3250 SoC. Signed-off-by:
Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by:
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Chanwoo Choi authored
This patch adds the new clock id for both UART2 and MM2 device for Exynos3250 SoC. Signed-off-by:
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Stefan Agner authored
The clock register are lost when enterying LPSTOPx, hence provide suspend/resume functions restoring them. The clock gates get restored by the individual driver, hence we do not need to restore them here. Signed-off-by:
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Stefan Agner authored
Signed-off-by:
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Stefan Agner authored
To use STOP mode without putting DDR3 into self-refresh mode, we need to keep the DDR clock enabled. Use the new gate configuration with a value of 2 to make sure that the clock is enabled in RUN, WAIT and STOP mode. Signed-off-by:
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Stefan Agner authored
The 2-bit gates found i.MX and Vybrid SoC support different clock configuration: 0b00: clk disabled 0b01: clk enabled in RUN mode but disabled in WAIT and STOP mode 0b10: clk enabled in RUN, WAIT and STOP mode (only Vybrid) 0b11: clk enabled in RUN and WAIT mode For some clocks, we might want to configure different behaviour, e.g. a memory clock should be on even in STOP mode. Add a new function imx_clk_gate2_cgr which allow to configure specific gate values through the cgr_val parameter. Signed-off-by:
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Fabio Estevam authored
SAIx and SAIx_IPG share the same bit fields in the CCM registers, so we should better register them via imx_clk_gate2_shared(). Signed-off-by:
Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by:
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- 29 Mar, 2016 1 commit
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git://github.com/anholt/linuxStephen Boyd authored
This pull request against clk/clk-next brings in fixes for fractional clocks on 2835, add the PCM clock that used to be driven directly by the bcm2835-i2s driver (that driver has been broken since this driver was introduced), and adds many other new clocks. * tag 'bcm2835-clk-next-2016-03-17' of git://github.com/anholt/linux: clk: bcm2835: add missing osc and per clocks clk: bcm2835: add missing PLL clock dividers clk: bcm2835: enable management of PCM clock clk: bcm2835: reorganize bcm2835_clock_array assignment clk: bcm2835: remove use of BCM2835_CLOCK_COUNT in driver clk: bcm2835: expose raw clock-registers via debugfs clk: bcm2835: clean up coding style issues clk: bcm2835: correctly enable fractional clock support clk: bcm2835: divider value has to be 1 or more clk: bcm2835: add locking to pll*_on/off methods clk: bcm2835: pll_off should only update CM_PLL_ANARST
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