1. 01 Feb, 2005 6 commits
    • Nicolas Pitre's avatar
      [ARM PATCH] 2443/1: enable iWMMXt on EABI binaries · 2677809c
      Nicolas Pitre authored
      Patch from Nicolas Pitre
      
      It appears that the EF_ARM_SOFT_FLOAT is a reserved bit with the new
      ARM EABI.  Since EABI is said to not support FPA (FPA emulation being
      the reason why we'd want to disable iWMMXt access) we now test for any
      EABI version as well to turn on iWMMXt access.
      
      Signed-off-by: Nicolas Pitre
      Signed-off-by: Russell King
      2677809c
    • Nicolas Pitre's avatar
      [ARM PATCH] 2430/3: TLS support for ARM · f5e58aa1
      Nicolas Pitre authored
      Patch from Nicolas Pitre
      
      This implements TLS support in the most efficient way for all ARM
      processors in use today.  The trick is to define a specific address in
      kernel area that is made readable from user space to hold the TLS
      pointer so it is highly efficient to retrieve it with no overhead.
      Since the kernel already maps a page at 0xffff0000 to hold the exception
      vectors, we can use the top of that page for storing the TLS ptr at
      0xffff0ffc. This address has the advantage of fitting optimally with the
      ARM load addressing mode as follows:
      	mov	rd, #0xffff0fff
      	ldr	rd, [rd, #-3]
      Considering load scheduling, this means 2 cycles to retrieve the TLS
      value which is even faster than a coprocessor access.  Even gcc
      generates the above assembly when given:
      	void *tls = *((void **)0xffff0ffc);
      This is fine to make the vector page readable from user space since it
      contains nothing that could compromize security and doesn't require an
      extra memory page to be allocated.
      On SMP (which should be ARMv6 and above only) the special reg for
      TLS will be available.  Since ARMv6 binaries are most likely to use
      strex/ldrex insns instead of swp to implement user space atomic
      primitives, those ARMv6 binaries won't execute on pre ARMv6 processors
      anyway.  So the abscence of a tls reg is a non issue for them already.
      Also on SMP targets, since the hivec page can't be relied upon to get
      the TLS value, we'll have the kernel emulate access to it through the
      data abort vector for backward compatibility with pre ARMv6 binaries.
      Otherwise, non SMP ARMv6 kernels will support both methods
      simultaneously.
      So the decision to use hivec or tlsreg could depend on whether given
      library is optimized for ARMv6+ or not. And since ARM SMP devices are
      still far from becoming mainstream we can safely go with the hivec (and
      hivec emulation on SMP) for the time being.
      
      Signed-off-by: Nicolas Pitre
      Signed-off-by: Russell King
      f5e58aa1
    • Russell King's avatar
      [ARM] Remove adrsvc macro. · 186bbc72
      Russell King authored
      The adrsvc macro was used to allow the entry-* files to be built on
      ARM32 and ARM26 processors.  Since we no longer support ARM26 CPUs,
      eliminate this macro.
      186bbc72
    • Richard Purdie's avatar
      [ARM PATCH] 2428/1: PXA Corgi - Add Backlight Device Definition · 87976c04
      Richard Purdie authored
      Patch from Richard Purdie
      
      Add a device definition to enable the backlight on the corgi
      machines (Sharp SL-C7xx series).
      [The backlight driver has been submitted to linux-fbdev-devel]
      [Applies after 2426/1]
      
      Signed-off-by: Richard Purdie
      Signed-off-by: Russell King
      87976c04
    • Richard Purdie's avatar
      [ARM PATCH] 2429/1: PXA Corgi - Bugfix + Cleanups · 89b07be1
      Richard Purdie authored
      Patch from Richard Purdie
      
      PXA Corgi - Bugfix + Cleanups:
      * Make sure the MMC timer init is called *before* enabling the
        interrupt (thanks Nicholas for pointing this out).
      * Add externs for the exported ssp functions
      * Finish commenting Corgi specific GPIOs
      [Applies after 2428/1]
      
      Signed-off-by: Richard Purdie
      Signed-off-by: Russell King
      89b07be1
    • George T. Joseph's avatar
      [ARM PATCH] 2434/1: Adds new machine: ixp4xx based gtwx5715 · 839e6624
      George T. Joseph authored
      Patch from George Joseph
      
      Machine number 641 already assigned.
      Changes...
      arch/arm/boot/compressed/head-xscale.S
      arch/arm/mach-ixp4xx/Kconfig
      arch/arm/mach-ixp4xx/Makefile
      include/asm-arm/arch-ixp4xx/uncompress.h
      Adds...
      arch/arm/mach-ixp4xx/gtwx5715-pci.c
      arch/arm/mach-ixp4xx/gtwx5715-setup.c
      include/asm-arm/arch-ixp4xx/gtwx5715.h
      Includes changes requested by Russell King
      
      Signed-off-by: George T Joseph
      Signed-off-by: Deepak Saxena
      Signed-off-by: Russell King
      839e6624
  2. 31 Jan, 2005 2 commits
  3. 30 Jan, 2005 3 commits
  4. 29 Jan, 2005 5 commits
  5. 28 Jan, 2005 10 commits
    • Martins Krikis's avatar
      [PATCH] fix an oops in ata_to_sense_error · 92dc2e37
      Martins Krikis authored
      Signed-off-by: default avatarJeff Garzik <jgarzik@pobox.com>
      92dc2e37
    • Andries E. Brouwer's avatar
      [PATCH] document atkbd.softraw · c923dd8b
      Andries E. Brouwer authored
      Document atkbd.softraw (and shorten a few long lines nearby).
      c923dd8b
    • Linus Torvalds's avatar
      Merge bk://bk.arm.linux.org.uk/linux-2.6-rmk · c56b4bcb
      Linus Torvalds authored
      into ppc970.osdl.org:/home/torvalds/v2.6/linux
      c56b4bcb
    • Wim Van Sebroeck's avatar
      [WATCHDOG] i8xx_tco.c-ICH4/6/7-patch · 23a3e707
      Wim Van Sebroeck authored
      Added support for the ICH4-M, ICH6, ICH6R, ICH6-M, ICH6W and ICH6RW
      chipsets. Also added support for the "undocumented" ICH7.
      23a3e707
    • Russell King's avatar
      [ARM] [1/4] Introduce svc_entry macro for common entry code · 99355085
      Russell King authored
      This is the first of 4 patches which factor out common code in
      the ARM exception entry assembly code, aiming towards a reduction
      in the size of the changes required here for SMP support.  These
      patches are low impact, and will be merged over the coarse of the
      next 4 days.
      
      This patch addresses the code handling exception entry from
      supervisor (kernel) mode.
      99355085
    • Marc Singer's avatar
      [ARM PATCH] 2442/1: Simplifying NODES_SHIFT · 9d46f44c
      Marc Singer authored
      Patch from Marc Singer
      
      The special case for the Sharp LH processors is unnecessary.  A macro
      override makes it cleaner and concentrates the change where it ought
      to be.  The default in include/asm-arm/numnodes.h means that only
      platforms that care to change the default need to do anything.
      
      Signed-off-by: Marc Singer
      Signed-off-by: Russell King
      9d46f44c
    • Ben Dooks's avatar
      [ARM PATCH] 2440/1: S3C2410 - serial auto-flow-control enable · ce9c2dcc
      Ben Dooks authored
      Patch from Ben Dooks
      
      Patch from Shannon Holland
      Enable automatic flow control if requested.
      
      Signed-off-by: Shannon Holland
      
      Signed-off-by: Ben Dooks
      Signed-off-by: Russell King
      ce9c2dcc
    • Ben Dooks's avatar
      [ARM PATCH] 2439/1: S3C2410 - serial driver parity selection · dfe9b780
      Ben Dooks authored
      Patch from Ben Dooks
      
      Patch from Dimitry Andric.
      The s3c2410 serial driver selects the opposite parity
      mode if parity is enabled.
      
      Signed-off-by: Dimitry Andric
      
      Signed-off-by: Ben Dooks
      Signed-off-by: Russell King
      dfe9b780
    • Ben Dooks's avatar
      [ARM PATCH] 2438/1: S3C2410 - fix IO address calculations · 2e0b3d0e
      Ben Dooks authored
      Patch from Ben Dooks
      
      Patch from Dimitry Andric.
      The include/asm-arm/arch-s3c2410/io.h file converts
      PC style port addresses to real ARM addresses, and
      needs to return an `void __iomem *` to avoid a number
      of warnings:
        CC      drivers/ide/ide-iops.o
      drivers/ide/ide-iops.c: In function `ide_insw':
      drivers/ide/ide-iops.c:49: warning: passing arg 1 of `__raw_readsw' makes pointer from integer without a cast
      drivers/ide/ide-iops.c: In function `ide_insl':
      drivers/ide/ide-iops.c:59: warning: passing arg 1 of `__raw_readsl' makes pointer from integer without a cast
      drivers/ide/ide-iops.c: In function `ide_outsw':
      drivers/ide/ide-iops.c:79: warning: passing arg 1 of `__raw_writesw' makes pointer from integer without a cast
      drivers/ide/ide-iops.c: In function `ide_outsl':
      drivers/ide/ide-iops.c:89: warning: passing arg 1 of `__raw_writesl' makes pointer from integer without a cast
        CC      lib/iomap.o
      lib/iomap.c: In function `ioread8_rep':
      lib/iomap.c:140: warning: passing arg 1 of `__raw_readsb' makes pointer from integer without a cast
      lib/iomap.c: In function `ioread16_rep':
      lib/iomap.c:144: warning: passing arg 1 of `__raw_readsw' makes pointer from integer without a cast
      lib/iomap.c: In function `ioread32_rep':
      lib/iomap.c:148: warning: passing arg 1 of `__raw_readsl' makes pointer from integer without a cast
      lib/iomap.c: In function `iowrite8_rep':
      lib/iomap.c:156: warning: passing arg 1 of `__raw_writesb' makes pointer from integer without a cast
      lib/iomap.c: In function `iowrite16_rep':
      lib/iomap.c:160: warning: passing arg 1 of `__raw_writesw' makes pointer from integer without a cast
      lib/iomap.c: In function `iowrite32_rep':
      lib/iomap.c:164: warning: passing arg 1 of `__raw_writesl' makes pointer from integer without a cast
      
      Signed-off-by: Dimitry Andric
      
      Signed-off-by: Ben Dooks
      Signed-off-by: Russell King
      2e0b3d0e
    • Linus Torvalds's avatar
      Merge bk://linux-scsi.bkbits.net/scsi-for-linus-2.6 · 842ca9a3
      Linus Torvalds authored
      into ppc970.osdl.org:/home/torvalds/v2.6/linux
      842ca9a3
  6. 27 Jan, 2005 2 commits
  7. 28 Jan, 2005 1 commit
  8. 27 Jan, 2005 11 commits