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- 11 Nov, 2012 36 commits
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Daniel Vetter authored
This essentially reverts commit cb0953d7 Author: Adam Jackson <ajax@redhat.com> Date: Fri Jul 16 14:46:29 2010 -0400 drm/i915: Initialize LVDS and eDP outputs before anything else simply because it doesn't scale: It misses SDVO and DVO panels, and now with DDI encoders on haswell this is becoming unmanageable. Instead we simply sort the connector list after everything is set up. Reviewed-by: Adam Jackson <ajax@redhat.com> Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Paulo Zanoni authored
On Haswell/LPT we must disable the PCH transcoder before we disable the FDI, so don't check for disabled FDI there. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Paulo Zanoni authored
This function is only for the previous gens. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Paulo Zanoni authored
These workarounds are documented on the CRT mode set sequence. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Paulo Zanoni authored
... instead of "pipe", which is wrong. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Paulo Zanoni authored
... instead of PIPECONF_INTERLACE_MASK. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> [danvet: applied the change by hand due to patch reorder.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Paulo Zanoni authored
That function is made for IBX. Running it on LPT will trigger tons of "unclaimed register" errors. The only port remaining on LPT is PCH_ADPA. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Paulo Zanoni authored
Because we already set all the bits we can set. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> [danvet: apply by hand due to dropped patch. Also, obey my OCD a bit and do a s/_TRANSACONF/TRANSCONF(TRANSCODER_A)/, makes it more consisten with other lpt pch code imnsho ...] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Paulo Zanoni authored
... instead of using "pipe". As already explained in previous commits, since Haswell/LPT cpu_transcoder, pch_transcoder and pipe are not the same thing. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Paulo Zanoni authored
These asserts are specific to IBX/CPT/PPT. Inside the assert_pch_pll function we even "return" in case we detect LPT, but I prefer to just not call it. In the future we might rename to something like ibx_assert_pch_pll. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Paulo Zanoni authored
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Paulo Zanoni authored
Since now we have lpt_enable_pch_transcoder. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Paulo Zanoni authored
For now the new functions are just copies. Differences will be added later. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Paulo Zanoni authored
To ironlake_{en,dis}able_pch_transcoder since these functions will be different on Haswell/LPT and since the "transcoder" they {en,dis}able is on the PCH. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> [danvet: again a small conflict because the fdi disable sequenc looks a bit different here.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Paulo Zanoni authored
On Haswell/LPT, pipe, cpu_transcoder and pch_transcoder are different things with different values, unlinke the previous gens. So here we use the right thing at the right place. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> [danvet: apply the patch by hand due to the reorder patch sequence. We also can't kill all uses of pipe where we should, since the fdi link train code isn't fixed up yet on this baselin.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Paulo Zanoni authored
There is no LVDS, so don't poke the LVDS registers. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Paulo Zanoni authored
This is just wrong. The lpt_program_iclkip should disable the PCH pixel clocks (and yes, we plan to rename it later). Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Paulo Zanoni authored
Because this function is only for the older PCHs, not the newer ones. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Paulo Zanoni authored
Since this function will only run on Haswell/LPT and newer. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Paulo Zanoni authored
Since now we have lpt_pch_enable for them. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Paulo Zanoni authored
For now it's just a fork of ironlake_pch_enable. The next commits will change this. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Daniel Vetter authored
Makes more sense to group the entire mode_set stage into one function. Noticed while discussiing the rather confusing set of function names with Paulo Zanoni. Unfortunately I don't have an idea to make the function names lesss confusion. v2: Use for_each_encoder_on_crtc as suggested by Chris Wilson. Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Ville Syrjälä authored
Refactor the code that stores the panning x/y position into the sarea. This also changes the code so that it won't mistakenly update sareaB_x/y for pipe >= C. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Ville Syrjälä authored
The current code can't deal with framebuffers with an offset. Return an error when trying to create such a framebuffer until the rest of the code is fixed to handle them. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Ville Syrjälä authored
Make sure the the framebuffer stride is smaller than 32k. That seems to be the limit on recent hardware. Not quite sure if <=Gen4 has smaller limits. Also when using a tiled memory make sure the object stride matches the framebuffer stride. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Ville Syrjälä authored
Fix support for all RGB/BGR pixel formats (except the 16:16:16:16 float format). Fix intel_init_framebuffer() to match hardware and driver limitations: * RGB332 is not supported at all * CI8 is supported * XRGB1555 & co. are supported on Gen3 and earlier * XRGB210101010 & co. are supported from Gen4 onwards * BGR formats are supported from Gen4 onwards * YUV formats are supported from Gen5 onwards (driver limitation) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Damien Lespiau authored
We were writing DSP_ADDR and DSP_SURF unconditionally. This did not trigger an unclaimed write before HSW as the address of DSP_ADDR has been repurposed as DSP_LINOFF. On HSW, though, DSP_LINOFF has been removed and then writting to it triggers an unclaimed write. This patch writes to DSP_ADDR or DSP_SURF to flush the display plane configuration depending on the gen we're running on. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Damien Lespiau authored
Just like in: commit c2c75131 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Thu Jul 5 12:17:30 2012 +0200 drm/i915: adjust framebuffer base address on gen4+ but this time, for the sprite planes. This ensures that the sprite offset are always inside the supported hardware limits since it becomes the offset into a page and we adjust the base address to a page boundary. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Damien Lespiau authored
Haswell consolidates DSP_TILEOFF and DSP_LINOFF into DSP_OFFSET (aka PRI_OFFSET). Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Daniel Vetter authored
And properly toggle the chicken bit in the pch to enable/disable fdi C rx. If we don't set this bit correctly, the rx gets confused in link training, which can result in an fdi link that silently fails to train the link (since the corresponding register reports success). Note that both fdi link B and C can suffer when this bit is not set correctly. The code as-is has a few deficiencies: - We presume all pipes use the pch which is not the case for cpu edp. - We don't bother with disabling both pipes when we could make things work, e.g. when pipe B switched from 4 to 2 lanes due to a mode change, we don't bother updating the w/a bit. - It's ugly. All of these are because we compute ->fdi_lanes way too late, when we're already setting up individual pipes. We need to have this information in ->modeset_global_resources already, to set things up correctly. But that is a much larger reorg of the code. Note that we actually hit the 2 lanes limit in practice rather quickly: Even though the 1920x1200 mode native mode of my screen fits into 2 lanes, it needs 3 lanes for the 1920x1080 (since that somehow has much more blanking ...). Not obeying this restriction seems to results in cute-looking digital noise. v2: Only ever clear the chicken bit when both pipes are off. v3: Use the new ->modeset_global_resources callback. v4: Move the WARNs to the right place. Oh how I hate hacks. v5: Fix spelling, noticed by Paulo Zanoni. Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Daniel Vetter authored
After all relevant pipes are disabled and after we've updated all the state with the staged state, but before we call the per-crtc ->mode_set functions there's a very natural point to set up any shared/global resources like - shared plls (obviously only the setup, the enabling needs to be separately handling with a separate refcount) - global watermark state like the DSPARB on gmch platforms - workaround bits that depend upon the exact global output configuration - enabling the right set of refclocks - enabling/disabling manual power wells. Now for a lot of these things we can't move them into this function yet, most often because we only compute the required information in the per-crtc ->mode_set callback. Which is too late. But due to a bunch of reasons (check-only atomic modeset, fastboot&hw state checks, ...) we need to separate the computation of that state from the actual hw frobbery anyway. So we can move things into this new callback step- by-step. Others can't be moved here (or implemented at all) because our code lacks the smarts to properly update them. E.g. the DSPARB can only be updated when all pipes are disabled, so if we decide to change it's value, we need to disable _all_ pipes. The infrastructure for that is already in place (with the various pipe masks that driver the modeset logic). But again we need to move a few things out of ->mode_set first before we can even implement the correct decision making. In any case, we need to start somewhere, so let's start with the callback: Some small follow-up patches will make immediate good use of it. Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Daniel Vetter authored
Since it is one. We need to move this code to encoder specific callbacks eventually, to kill all that inversion of control ... Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Daniel Vetter authored
Atm we have a few funny issues where we enable/disable shared pll clocks. To make it clear that we are not required to enable/ disable the pch plls together with the other pch resources (and so should keep it running when it's used by another pipe in a shared pll configuration) add a comment. This note is lifted from "Graphics BSpec: vol4g North Display Engine Registers [IVB], Display Mode Set Sequence", step 9.d. of the enable sequence: "Configure and enable PCH DPLL, wait for PCH DPLL warmup (Can be done anytime before enabling PCH transcoder)." Since fixing the pll sharing code to no longer disable shared plls if they're still in use is more involved, let's just stick with the comment for now. v2: Make the comment in the code clearer, to address questions raised by Paulo Zanoni in review. Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Daniel Vetter authored
My machine here has the correct ones already, but better safe than sorry. IBX has different settings for that register, and on IBX the device defaults match the recommended values. Hence I did not add the respective writes for IBX. LPT needs the same settings, but that has been done already commit 4acf5186 Author: Eugeni Dodonov <eugeni.dodonov@intel.com> Date: Wed Jul 4 20:15:16 2012 -0300 drm/i915: program FDI_RX TP and FDI delays Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Daniel Vetter authored
For reference, see "Graphics BSpec: vol4g North Display Engine Registers [IVB], Display Mode Set Sequence", step 4 of the enabling sequence: a. "Enable PCH FDI Receiver PLL, wait for warmup plus DMI latency b. "Switch from Rawclk to PCDclk in FDI Receiver c. "Enable CPU FDI Transmitter PLL, wait for warmup" Cc: Paulo Zanoni <przanoni@gmail.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Daniel Vetter authored
According to "Graphics BSpec: vol4g North Display Engine Registers [IVB], Display Mode Set Sequence" We need to write the TU size register of the fdi RX unit _before_ starting to train the link. Note: The current code is actually correct as Paulo mentioned in review, but it's a bit confusion since only the fdi rx/tx plls need to be enabled before the cpu pipes/planes. Hence it's still a good idea to move the TU_SIZE setting to the "right" spot in the sequence, to better match Bspec. Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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- 02 Nov, 2012 1 commit
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Jani Nikula authored
Daniel's backmerge commit c2fb7916 Merge: 29de6ce5 6f0c0580 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Mon Oct 22 14:34:51 2012 +0200 Merge tag 'v3.7-rc2' into drm-intel-next-queued to solve conflicts blew up (either git or Daniel was trying to be too clever for their own good; it's usually convenient to blame tools ;) and caused the changes of commit 0c96c65b Author: Jani Nikula <jani.nikula@intel.com> Date: Wed Sep 26 18:43:10 2012 +0300 drm/i915: use adjusted_mode instead of mode for checking the 6bpc force flag in ironlake_crtc_mode_set() to be dropped. Fix the call in ironlake_crtc_mode_set() again, and while at it, also fix the new, copy-pasted haswell_crtc_mode_set() to use adjusted_mode. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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- 26 Oct, 2012 3 commits
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Paulo Zanoni authored
See the documentation for the DDI_FUNC_CTL register, EDP Input Select bits: when the EDP input selection is B, the VTOTAL_B must be programmed with the VTOTAL_EDP value, same thing for selection C. V2: Use I915_READ as suggested by Daniel Vetter. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Paulo Zanoni authored
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Paulo Zanoni authored
Same thing as the previous commits. Not renaming this one since it exists since way before Haswell. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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